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Circuitos integrados HDMI, DisplayPort y MIPI

SN65DSI86-Q1

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SN65DSI86-Q1

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Detalles del producto

Type Bridge Protocols MIPI DSI, eDP Rating Automotive Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
Type Bridge Protocols MIPI DSI, eDP Rating Automotive Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
HTQFP (PAP) 64 144 mm² 12 x 12
  • Embedded DisplayPort (eDP) 1.4 Compliant
    Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR),
    2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24
    Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY Version 1.1 Physical
    Layer Front-End and Display Serial Interface (DSI)
    Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One,
    Two, Three, or Four D-PHY Data Lanes Per
    Channel Operating up to 1.5 Gbps Per Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets
    With RGB666 and RGB888 Formats
  • Suitable for 60 fps 4K 4096 × 2304 Resolution at
    18 bpp Color, and WUXGA 1920 × 1200
    Resolution with 3D Graphics at 60 fps (120 fps
    Equivalent)
  • MIPI Front-End Configurable for Single-Channel
    or Dual-Channel DSI Configuration
  • Supports Dual-Channel DSI Odd, Even and Left,
    Right Operating Modes
  • 1.2-V Main VCC Power Supply and 1.8-V Supply
    for Digital I/Os
  • Low-Power Features Include Panel Refresh and
    MIPI Ultralow Power State (ULPS) Support
  • DisplayPort Lane Polarity and Assignment
    Configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz,
    and 38.4-MHz Frequencies Through External
    Reference Clock (REFCLK)
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-Terminal HTQFP (PAP)
  • Temperature Range: –40°C to +85°C
  • Embedded DisplayPort (eDP) 1.4 Compliant
    Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR),
    2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24
    Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY Version 1.1 Physical
    Layer Front-End and Display Serial Interface (DSI)
    Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One,
    Two, Three, or Four D-PHY Data Lanes Per
    Channel Operating up to 1.5 Gbps Per Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets
    With RGB666 and RGB888 Formats
  • Suitable for 60 fps 4K 4096 × 2304 Resolution at
    18 bpp Color, and WUXGA 1920 × 1200
    Resolution with 3D Graphics at 60 fps (120 fps
    Equivalent)
  • MIPI Front-End Configurable for Single-Channel
    or Dual-Channel DSI Configuration
  • Supports Dual-Channel DSI Odd, Even and Left,
    Right Operating Modes
  • 1.2-V Main VCC Power Supply and 1.8-V Supply
    for Digital I/Os
  • Low-Power Features Include Panel Refresh and
    MIPI Ultralow Power State (ULPS) Support
  • DisplayPort Lane Polarity and Assignment
    Configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz,
    and 38.4-MHz Frequencies Through External
    Reference Clock (REFCLK)
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-Terminal HTQFP (PAP)
  • Temperature Range: –40°C to +85°C

The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.

The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.

In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.

The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.

The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.

In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.
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Documentación técnica

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* Data sheet SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge datasheet (Rev. A) PDF | HTML 29 dic 2015
Application note SN65DSI86 and SN65DSI96 Hardware Implementation Guide 08 oct 2013

Diseño y desarrollo

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La herramienta de configuración de video del sintonizador DSI genera la sincronización de video y los valores de registro de configuración necesarios para transferir los datos DSI al panel LVDS mediante el dispositivo de puente DSI a LVDS SN65DSI8x. El tiempo y los valores de (...)
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Modelo de simulación

SN65DSI86-Q1 IBIS Model

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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HTQFP (PAP) 64 Ver opciones
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