These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high
transition of the clock (CLK) input when the enable (
) input is low. Data can be read
back onto the data inputs by taking the read (
) input low, in addition to having
low. When EN\ is high, both the
read-back and write modes are disabled. Transitions on should only be made with CLK high
to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity
(T/C\) input. When T/C\ is high, Q is the same as is stored in the
flip-flops. When T/C\ is low, the output data is inverted. The Q
outputs can be placed in the high-impedance state by taking the
output-enable (
) input high.
does not
affect the internal operation of the register. Old data can be
retained or new data can be entered while the outputs are off.
A low level at the clear (
)
input resets the internal registers low. The clear function is
asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit D-Type Edge-Triggered Read-Back Latches datasheet (Rev. B) | 01 ene 1995 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 dic 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 ago 1995 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| SOIC (DW) | 24 | Ver opciones |
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