SN74AUP1G240

Name: SN74AUP1G240
Brand: TI
SKU: SN74AUP1G240
Price: 0.087 USD

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Inversor único de baja potencia, de 0.8 V a 3.6 V, con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74AUP1G240 Low-Power Single Inverter With 3-State Output datasheet (Rev. D) (Inglés) PDF | HTML

SN74AUP1G240

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Detalles del producto

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

1

IOL (max) (mA)

4

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

AUP

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

1

IOL (max) (mA)

4

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

AUP

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

5

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

USON (DRY)

6

1.45 mm² 1.45 x 1

X2SON (DPW)

5

0.64 mm² 0.8 x 0.8

X2SON (DSF)

6

1 mm² 1 x 1

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
- I_CC = 0.9 µA Maximum
Low Dynamic-Power Consumption
- C_pd = 4.2 pF at 3.3 V Typical
Low Input Capacitance
- C_I = 1.5 pF Typical
Low Noise – Overshoot and Undershoot
<10% of V_CC
Input-Disable Feature Allows Floating Input Conditions
I_off Supports Partial Power-Down-Mode Operation
Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.7 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
- I_CC = 0.9 µA Maximum
Low Dynamic-Power Consumption
- C_pd = 4.2 pF at 3.3 V Typical
Low Input Capacitance
- C_I = 1.5 pF Typical
Low Noise – Overshoot and Undershoot
<10% of V_CC
Input-Disable Feature Allows Floating Input Conditions
I_off Supports Partial Power-Down-Mode Operation
Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.7 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family ).

This buffer/driver is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To assure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family ).

This buffer/driver is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To assure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	SN74AUP1G240 Low-Power Single Inverter With 3-State Output datasheet (Rev. D)	PDF \| HTML	12 oct 2017
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	22 may 2019
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 jul 2018
	Application note	Designing and Manufacturing with TI's X2SON Packages		23 ago 2017
	Selection guide	Logic Guide (Rev. AB)		12 jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 jul 2016
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 jul 2004

Diseño y desarrollo

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Placa de evaluación

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Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.

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