SN74LVTH241

Name: SN74LVTH241
Brand: TI
SKU: SN74LVTH241
Price: 0.276 USD

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Búferes de 8 canales, 2.7 V a 3.6 V con retención de bus, entradas CMOS compatibles con TTL y salida

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document-pdfAcrobat SN54LVTH241, SN74LVTH241 datasheet (Rev. K) (Inglés)

SN74LVTH241

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Detalles del producto

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Number of channels

8

IOL (max) (mA)

64

Supply current (max) (µA)

5000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Number of channels

8

IOL (max) (mA)

64

Supply current (max) (µA)

5000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH241 devices are organized as two 4-bit line drivers with separate output-enable (1OE\, 2OE) inputs. When 1OE\ is low or 2OE is high, the devices pass noninverted data from the A inputs to the Y outputs. When 1OE\ is high or 2OE is low, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH241 devices are organized as two 4-bit line drivers with separate output-enable (1OE\, 2OE) inputs. When 1OE\ is low or 2OE is high, the devices pass noninverted data from the A inputs to the Y outputs. When 1OE\ is high or 2OE is low, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	SN54LVTH241, SN74LVTH241 datasheet (Rev. K)	13 oct 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)	17 sep 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 may 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 may 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 ene 2001
	Application note	LVT-to-LVTH Conversion	08 dic 1998
	Application note	LVT Family Characteristics (Rev. A)	01 mar 1998
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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