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Microcontroladores (MCU) y procesadores
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Sistemas automotrices SoC de asistencia al conductor

TDA4APE-Q1

ACTIVO

SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA y C7xDSP para percepción y análisis de visión

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TDA4APE-Q1

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Detalles del producto

CPU 4 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, 2 DSI, MIPI DPI Protocols Ethernet PCIe 1 PCIe Gen 3 Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
CPU 4 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, 2 DSI, MIPI DPI Protocols Ethernet PCIe 1 PCIe Gen 3 Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (AND) 1063 729 mm² 27 x 27

Processor cores:

  • Up to Three C7x floating point, vector DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
  • Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
  • Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 2x32-b bus with inline ECC up to 34GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL-D/SIL-3
    • Hardware integrity up to ASIL-D/SIL-3for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting 4 external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
  • Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Three C7x floating point, vector DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
  • Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
  • Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 2x32-b bus with inline ECC up to 34GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL-D/SIL-3
    • Hardware integrity up to ASIL-D/SIL-3for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting 4 external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
  • Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

The TDA4VPE-Q1 TDA4APE-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VPE-Q1 TDA4APE-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VPE-Q1 TDA4APE-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate four core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VPE-Q1 TDA4APE-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VPE-Q1 TDA4APE-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VPE-Q1 TDA4APE-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VPE-Q1 TDA4APE-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate four core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VPE-Q1 TDA4APE-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
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Documentación técnica

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* Data sheet TDA4VPE-Q1, TDA4APE-Q1 Jacinto™ Automotive Processors datasheet (Rev. B) PDF | HTML 03 nov 2025
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. B) PDF | HTML 24 jul 2024
* User guide J784S4 J742S2 Technical Reference Manual (Rev. E) PDF | HTML 18 sep 2025
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 01 oct 2025
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25 sep 2025
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17 jun 2025
Functional safety information J784S4: TDA4VH TDA4AH TDA4VP TDA4AP SN17 SN18, J742S2: TDA4VPE TDA4APE SN16 TÜV Functional Safety Certificate 11 jun 2025
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS (Rev. A) PDF | HTML 16 may 2025
User guide J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide (Rev. A) 23 dic 2024
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 ago 2024
User guide J784S4 J742S2 Technical Reference Manual (Rev. D) 24 jul 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 jun 2024
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14 may 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 abr 2024
Technical article Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 05 ene 2024
Technical article How to deliver current beyond 100 A to an ADAS processor PDF | HTML 04 ene 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 nov 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 mar 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 ene 2023
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 15 ago 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 abr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 abr 2022
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29 mar 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 ene 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 ene 2022
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 oct 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 jul 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 ene 2021
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 oct 2020
Application note OSPI Tuning Procedure PDF | HTML 08 jul 2020

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

J742S2XH01EVM — Módulo de evaluación TDA4VPE y TDA4APE

El módulo de evaluación (EVM) J742S2XH01EVM es una plataforma para evaluar los procesadores TDA4VPE-Q1 y TDA4APE-Q1 en aplicaciones de análisis de visión y redes en mercados industriales y automotrices. Estos procesadores funcionan bien sobre todo en aplicaciones de control de dominio de sistemas (...)

Guía del usuario: PDF | HTML
No disponible en TI.com
Sonda de depuración

LB-3P-TRACE32-ARM — Sistema de depuración y seguimiento Lauterbach TRACE32 para microcontroladores y procesadores basado

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of Arm®-based microcontrollers and processors. The globally renowned debug and trace solutions for embedded systems and SoCs are the perfect (...)

Desde: Lauterbach GmbH
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Sonda de depuración

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

Desde: TASKING Germany GmbH
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Kit de desarrollo de software (SDK)

J742S2-PROCESSOR-LINUX-SDK — Linux® SDK for TDA4APE-Q1 and TDA4VPE-Q1

The J742S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4APE-Q1 and TDA4VPE-Q1 system-on-a-chip (SoCs) within our Jacinto™ (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Sistemas automotrices SoC de asistencia al conductor
TDA4APE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA y C7xDSP para percepción y análisis de visión TDA4VPE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA, C7xDSP y GPU para percepción y análisis de vis
Opciones de descarga
Kit de desarrollo de software (SDK)

J742S2-PROCESSOR-QNX-SDK — QNX SDK for TDA4APE-Q1 and TDA4VPE-Q1

The J742S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4APE-Q1 and TDA4VPE-Q1 system-on-a-chip (SoCs) within our Jacinto™ (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Sistemas automotrices SoC de asistencia al conductor
TDA4APE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA y C7xDSP para percepción y análisis de visión TDA4VPE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA, C7xDSP y GPU para percepción y análisis de vis
Opciones de descarga
Software de aplicación y estructura

J742S2-SW — J742S2 software

Software packages for Processor SDK release
Productos y hardware compatibles

Productos y hardware compatibles

Productos
Sistemas automotrices SoC de asistencia al conductor
TDA4APE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA y C7xDSP para percepción y análisis de visión TDA4VPE-Q1 — SoC con Arm® Cortex®-A72 cuádruple, 16 TOPS de IA, C7xDSP y GPU para percepción y análisis de vis
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Firmware

USIT-3P-SECIC-HSM — Firmware Uni-Sentry SecIC-HSM

El SecIC-HSM está diseñado para cumplir con los requisitos de ciberseguridad necesarios para los chips MCU/SoC. El firmware HSM se puede aplicar en campos como automóviles, nuevas energías, fotovoltaica, robótica, salud y aviación. Las funciones de ciberseguridad proporcionadas disponibles incluyen (...)
Desde: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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Firmware

USIT-3P-SECIC-PQC — Firmware de algoritmos Uni-Sentry SecIC-PQC

Las soluciones de seguridad de Uni-Sentry adoptan algoritmos PQC capaces de resistir las amenazas de descifrado planteadas por los ordenadores cuánticos a los algoritmos criptográficos tradicionales. El firmware del PQC está cooptimizado con el Módulo de Seguridad de Hardware (HSM), aprovechando la (...)
Desde: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Productos y hardware compatibles

Productos y hardware compatibles

Este recurso de diseño es compatible con la mayoría de los productos de estas categorías.

Revise la página de detalles del producto para verificar la compatibilidad.
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Sistema operativo (SO)

WHIS-3P-SAFERTOS — RTOS de seguridad precertificado SAFERTOS de WITTENSTEIN

SAFERTOS® es un sistema operativo único en tiempo real diseñado para procesadores integrados. Está precertificado según las normas IEC 61508 SIL3 e ISO 26262 ASILD por TÜV SÜD. SAFERTOS® se diseñó específicamente para la seguridad por el equipo de expertos de WHIS y se usa globalmente en (...)
Desde: WITTENSTEIN High Integrity Systems
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Modelo de simulación

J742S2 BSDL Model

SPRM866.ZIP (16 KB) - BSDL Model
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Modelo de simulación

J742S2 IBIS Model

SPRM865.ZIP (1496 KB) - IBIS Model
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Modelo de simulación

J742S2 Thermal Model

SPRM864.ZIP (0 KB) - Thermal Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (AND) 1063 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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