74ACT11286
- Inputs Are TTL-Voltage Compatible
- Generates Either Odd or Even Parity for Nine Data Lines
- Cascadable for n-Bits Parity
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process - 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)
EPIC is a trademark of Texas Instruments Incorporated.
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
The 
control input
is implemented specifically to accommodate cascading. When the is low, the parity tree is
disabled and the PARITY ERROR output remains at a high logic level,
regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR
indicates a parity error when either an even number of inputs (A
through I) are high and PARITY I/O is forced to a low logic level, or
when an odd number of inputs are high and PARITY I/O is forced to a
high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from -40°C to 85°C.
技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | データシート | 9-Bit Parity Generator/Checker With Bus Driver Parity I/O Ports データシート (Rev. B) | 1996年 4月 1日 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点