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DS25BR101

アクティブ

送信プリエンファシス機能と受信イコライゼーション機能搭載、3.125Gbps、LVDS バッファ

ご注文はこちら
データシート

DS25BR101

アクティブ
データシート ご注文はこちら

製品詳細

Function Buffer, Equalizer Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer, Equalizer Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WSON (NGQ) 8 9 mm² (3 mm × 3 mm)
  • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
  • Receive Equalization Reduces ISI Jitter Due to Media Loss
  • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
  • On-Chip 100Ω Input and Output Termination:
    • Minimizes Insertion and Return Losses
    • Reduces Component Count
    • Minimizes Board Space
  • DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
  • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 3 mm x 3 mm WSON-8 Space Saving Package

All trademarks are the property of their respective owners.

  • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
  • Receive Equalization Reduces ISI Jitter Due to Media Loss
  • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
  • On-Chip 100Ω Input and Output Termination:
    • Minimizes Insertion and Return Losses
    • Reduces Component Count
    • Minimizes Board Space
  • DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
  • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 3 mm x 3 mm WSON-8 Space Saving Package

All trademarks are the property of their respective owners.

The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.

The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.
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DS25BR440 アクティブ 送信プリエンファシス機能と受信イコライゼーション機能搭載、3.125Gbps、クワッド LVDS バッファ Includes redriver and repeater function, additional transmitters and receivers (4T/4R)

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha & Rcve Equalization データシート (Rev. F) 2013/04/14
アプリケーション・ノート Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 2020/10/29
アプリケーション・ノート Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners 2019/06/29

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WSON (NGQ) 8 Ultra Librarian
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