SN75LVDS84
- 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput
- Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
- 21 Data Channels Plus Clock-In Low-Voltage TTL and 3 Data Channels Plus Clock-Out Low-Voltage Differential
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant Data Inputs
- ESD Protection Exceeds 6 kV
- SN75LVDS84 Has Falling-Clock Edge-Triggered Inputs
- Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
- Consumes Less Than 1 mW When Disabled
- Wide Phase-Lock Input Frequency Range:
- 31 MHz to 68 MHz
- No External Components Required for PLL
- Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Improved Replacement for the DS90C561
FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86.
When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS84 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level.
The SN75LVDS84 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | Flatlink Transmitters データシート (Rev. D) | 2007/11/06 | |||
| アプリケーション・ノート | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/09 | ||||
| アプリケーション・ノート | Flatlink Data Transmission System Design Overview (Rev. A) | 2001/06/01 | ||||
| アプリケーション・ノート | Time Budgeting of the Flatlink Interface Application Report | 1997/06/11 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |