CD54ACT374

Name: CD54ACT374
Brand: TI
SKU: CD54ACT374
Price: 10.9 USD

활성

3상 출력을 지원하는 8진 D형 플립플롭

지금 주문

데이터시트

document-pdfAcrobat CDx4AC374, CDx4ACT374, CD74AC534 Octal D-Type Flip-Flops, 3-State Positive-Edge Triggered datasheet (Rev. A) (영어) PDF | HTML

CD54ACT374

활성

데이터시트

지금 주문

제품 상세 정보

Number of channels

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

125

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

125

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

167.464 mm² 24.2 x 6.92

SCR-Latch-up-resistant CMOS process and circuit design
Speed of bipolar FAST*/AS/S with significantly reduced power consumption
Balanced propagation delays
AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply
± 24mA output drive current
- Fanout to 15 FAST* ICs
- Drives 50ohm transmission lines

⁽¹⁾FAST is a Registered Trademark of Fairchild Semiconductor Corp.

SCR-Latch-up-resistant CMOS process and circuit design
Speed of bipolar FAST*/AS/S with significantly reduced power consumption
Balanced propagation delays
AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply
± 24mA output drive current
- Fanout to 15 FAST* ICs
- Drives 50ohm transmission lines

⁽¹⁾FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The eight flip-flops of the ’AC374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

open-in-new

기타 D형 플립플롭 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능

신규 SN74LV2T74-EP

활성

클리어, 프리셋 및 통합 레벨 시프터를 지원하는 향상된 제품 듀얼 D형 플립플롭 Voltage range (1.65V to 5.5V), voltage translation capable

기술 문서

star

=TI에서 선정한 이 제품의 인기 문서

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모두 보기12

	유형	직함		날짜
*	Data sheet	CDx4AC374, CDx4ACT374, CD74AC534 Octal D-Type Flip-Flops, 3-State Positive-Edge Triggered datasheet (Rev. A)	PDF \| HTML	2024/03/22
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022/12/15
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	Designing With Logic (Rev. C)		1997/06/01
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		1996/04/01