홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

CD54HC273

활성

리셋을 지원하는 고속 CMOS 로직 8진 D형 플립플롭

지금 주문하기
데이터 시트

CD54HC273

활성
데이터 시트 지금 주문하기

제품 상세 정보

Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 23 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 23 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92
  • Common clock and asynchronous controller reset
  • Positive edge triggering
  • Buffered inputs
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types:
    • 2V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • 4.5V to 5.5V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1µA at VOL,VOH
  • Common clock and asynchronous controller reset
  • Positive edge triggering
  • Buffered inputs
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types:
    • 2V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • 4.5V to 5.5V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1µA at VOL,VOH

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.
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기술 자료

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* Data sheet CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset datasheet (Rev. D) PDF | HTML 2025/10/28

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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