홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 시프트 레지스터
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
시프트 레지스터

CD74HC4015

활성

고속 CMOS 로직 듀얼 4단계 정적 시프트 레지스터

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데이터 시트

CD74HC4015

활성
지금 주문하기

제품 상세 정보

Configuration Serial-in, Parallel-out Bits (#) 4 Technology family HC Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 4 Technology family HC Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25°C
  • Positive-Edge Clocking
  • Overriding Reset
  • Buffered Inputs and Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25°C
  • Positive-Edge Clocking
  • Overriding Reset
  • Buffered Inputs and Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.

The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types.

The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.

The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types.
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* 데이터 시트 CD54HC4015, CD74HC4015 datasheet (Rev. C) 2003. 5. 21

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