CDCLVD1204

활성

저지터, 2입력 선택 가능 1:4 범용-To-LVDS 버퍼

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데이터 시트

document-pdfAcrobat CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. C) (영어) PDF | HTML

CDCLVD1204

활성

지금 주문하기

제품 상세 정보

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGT)

16

9 mm² (3 mm × 3 mm)

2:4 differential buffer
Low additive jitter: <300fs RMS in 10kHz to 20MHz
Low output skew of 20ps (maximum)
Universal inputs accept LVDS, LVPECL, and LVCMOS
Selectable clock inputs through control pin
4 LVDS outputs, ANSI EIA/TIA-644A standard compatible
Clock frequency: up to 800MHz
Device power supply: 2.375V to 2.625V
LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 85°C
Packaged in 3mm × 3mm, 16-Pin VQFN (RGT)
ESD protection exceeds 3kV HBM, 1kV CDM

2:4 differential buffer
Low additive jitter: <300fs RMS in 10kHz to 20MHz
Low output skew of 20ps (maximum)
Universal inputs accept LVDS, LVPECL, and LVCMOS
Selectable clock inputs through control pin
4 LVDS outputs, ANSI EIA/TIA-644A standard compatible
Clock frequency: up to 800MHz
Device power supply: 2.375V to 2.625V
LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 85°C
Packaged in 3mm × 3mm, 16-Pin VQFN (RGT)
ESD protection exceeds 3kV HBM, 1kV CDM

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3mm × 3mm VQFN package.

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3mm × 3mm VQFN package.

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LMK1D1204

활성

4채널 출력 LVDS 1.8V 버퍼 Improved jitter performance and wider supported voltage range

비교 대상 장치와 유사한 기능.

LMK1D1204P

활성

핀 제어를 지원하는 4채널 출력 LVDS 1.8V, 2.5V 및 3.3V 버퍼 Improved jitter performance and wider supported voltage range with individual output enable/disable through pin control

LMK00304

활성

4개의 구성 가능한 출력을 지원하는 3.1GHz 차동 클록 버퍼/레벨 트랜스레이터 Ultra low additive jitter,1:4 Universal Differential Buffer that can support LVDS

기술 자료

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4개 모두 보기

상위 문서	유형	직함	형식 옵션
*	데이터 시트	CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. C)	PDF \| HTML	2026. 5. 14
	애플리케이션 노트	Sine to Square Wave Conversion Using Clock Buffers	PDF \| HTML	2024. 9. 3
	애플리케이션 노트	Clocking Design Guidelines: Unused Pins		2015. 11. 19
	사용 설명서	Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board		2010. 6. 14

설계 및 개발

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평가 보드

CDCLVD1204EVM — CDCLVD1204 평가 모듈

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)

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