CDCLVD2106

활성

저지터, 듀얼 1:6 범용-To-LVDS 버퍼

지금 주문하기

데이터 시트

document-pdfAcrobat Dual 1:6 Low Additive Jitter LVDS Buffer datasheet (Rev. B) (영어)

CDCLVD2106

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of outputs

12

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Dual 1:6 Differential Buffer
Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
Low Within Bank Output Skew of 45 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Six Outputs
Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

Dual 1:6 Differential Buffer
Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
Low Within Bank Output Skew of 45 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Six Outputs
Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.

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LMK1D2106

활성

듀얼 뱅크 6채널 출력 1.8V, 2.5V 및 3.3V LVDS 버퍼 Pin-to-pin upgrade with improved jitter, phase noise, and wider supported voltage range

비교 대상 장치와 유사한 기능.

LMK00301

활성

3GHz, 10개 출력의 차동 팬아웃 버퍼/레벨 변환기 Ultra low additive jitter,1:10 universal differential buffer that can support LVDS

기술 자료

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1개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	Dual 1:6 Low Additive Jitter LVDS Buffer datasheet (Rev. B)			2011. 1. 17

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평가 보드

CDCLVD2106EVM — CDCLVD2106 평가 모듈

The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)

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