홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 오디오 및 레이더 DSP SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
오디오 및 레이더 DSP SoC

DRA745

활성

차량 인포테인먼트 및 클러스터용 그래픽 및 DSP를 지원하는 듀얼 1.2GHz Arm Cortex-A15 SoC 프로세서

지금 주문
데이터 시트
사용자 가이드
정오표

DRA745

활성
데이터 시트 지금 주문

제품 상세 정보

CPU 2 Arm Cortex-A15 Frequency (MHz) 1176 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
CPU 2 Arm Cortex-A15 Frequency (MHz) 1176 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
filter 기타 오디오 및 레이더 DSP SoC 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
45개 모두 보기
유형 직함 날짜
* Data sheet DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 2019/05/07
* Errata DRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. K) PDF | HTML 2024/09/08
* User guide DRA75x, DRA74x Technical Reference Manual (SR2.0 & SR1.1) (Rev. H) PDF | HTML 2024/05/24
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/05/05
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/08/24
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/01/06
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/06/11
Application note Achieving Early CAN Response on DRA7xx Devices 2018/11/28
Application note DRA74x_75x/DRA72x Performance (Rev. A) 2018/10/31
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018/09/14
Application note The Implementation of YUV422 Output for SRV 2018/08/02
Application note MMC DLL Tuning (Rev. B) 2018/07/31
Application note Integrating AUTOSAR on TI SoC: Fundamentals 2018/06/18
Application note ECC/EDC on TDAxx (Rev. B) 2018/06/13
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018/06/12
Application note Sharing VPE Between VISIONSDK and PSDKLA 2018/05/04
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 2018/02/13
Application note Flashing Utility - mflash 2018/01/09
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017/11/30
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017/11/27
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/07
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/03
Application note Robust Rear-View Camera (RVC) App Report 2017/09/13
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/09/12
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017/08/14
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017/07/12
White paper Revolutionize the automotive cockpit 2017/06/02
Application note Linux Boot Time Optimizations on DRA7xx Devices 2017/03/31
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017/02/17
Application note Early Splash Screen on DRA7x Devices 2017/01/31
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
Application note Gstreamer Migration Guidelines 2016/04/26
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016/04/21
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016/04/21
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 2016/04/14
Application note Tools and Techniques for Audio Debugging 2016/04/13
Application note Debugging Tools and Techniques With IPC3.x 2016/03/30
Technical article Infotainment for the Masses – Volkswagen MIB II Standard powered by TI PDF | HTML 2016/02/17
User guide JAMR3 Tuner Application Board User’s Guide 2016/02/09
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016/01/15
Technical article Difficult to see. Always in motion is the future PDF | HTML 2016/01/04
Technical article Securing the Scene PDF | HTML 2015/12/16
Technical article What a journey: from Archimedes to reconfigurable clusters PDF | HTML 2015/11/23
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014/10/14
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/08/13

설계 및 개발

전원 공급 솔루션

DRA745에 사용 가능한 전원 공급 솔루션을 찾아보세요. TI는 칩(SoC), 프로세서, 마이크로컨트롤러, 센서 또는 FPGA(Field Programmable Gate Array)의 TI와 비TI 시스템을 위한 전원 공급 솔루션을 제공합니다.

솔루션 보기
평가 보드

J6EVM5777 — DRA7xx 평가 모듈

Jacinto™ DRA7xx 평가 모듈 플랫폼은 개발 작업의 속도를 높이고 인포테인먼트, 재구성 가능한 디지털 클러스터 또는 통합 디지털 콕핏 같은 애플리케이션의 출시 시간을 단축하도록 설계되었습니다. DRA74x 및 DRA75x Jacinto Infotainment SoC 전반에서 확장성과 재사용이 가능하도록 설계된 이 EVM은 Jacinto DRA75x SoC를 기반으로 하며, 이 SoC는 확장 가능한 이기종 아키텍처를 포함합니다. 해당 아키텍처는 두 개의 ARM® Cortex®-A15 코어, 두 개의 ARM Cortex-M4 (...)

발송: SVTRONICS INC
사용 설명서: PDF
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평가 보드

J6PEVM577P — DRA7xP 평가 모듈

DRA77xP/DRA76xP-ACD는 DRA77xP 및 DRA76xP JacintoTM Infotainment System-on-Chips(SoCs) 전체에서 확장과 재사용이 가능하도록 설계된 평가 플랫폼으로, 2개의 ARM Cortex-A15 마이크로프로세서 유닛, 2개의 Arm® Cortex®-M4 처리 하위시스템이 혼합된 확장 가능한 이기종 아키텍처를 통합한 Jacinto DRA77xP SoC를 기반으로 합니다. 각각 2개의 ARM Cortex 마이크로프로세서, 2개의 디지털 신호 프로세서(DSPC66x), 2개의 (...)

발송: SVTRONICS INC
사용 설명서: PDF
파트너 사이트 방문
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-DRA7X — DRA7x Jacinto™ 프로세서용 프로세서 소프트웨어 개발 키트 – Linux, Android 및 RTOS

Processor SDK Linux Automotive

Processor SDK Linux Automotive는 TI의 인포테인먼트 SoC의 Jacinto™ DRAx 제품군을 위한 기본 소프트웨어 개발 플랫폼입니다. 소프트웨어 프레임 워크를 통해 사용자는 차세대 자동차를 위한 기능이 풍부한 인포테인먼트 솔루션(재구성 가능한 디지털 계기판, 통합 콕핏, 차량 내 인포테인먼트, 텔레매틱스, 뒷좌석 엔터테인먼트 등)을 개발할 수 있습니다. SDK는 일반적인 Processor SDK 플랫폼을 기반으로 합니다.

주요 내용
  • (...)
사용 설명서: PDF
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운영 체제(OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
발송: Green Hills Software
파트너 사이트 방문
지원 소프트웨어

VCTR-3P-MICROSAR — 마이크로컨트롤러 및 고성능 컴퓨터(HPC)용 벡터 MICROSAR AUTOSAR 소프트웨어

MICROSAR 및 DaVinci 제품군은 정교한 임베디드 소프트웨어 및 마이크로 컨트롤러 및 HPC를 위한 강력한 개발 툴로 ECU 개발을 간소화합니다. 고급 인프라 소프트웨어를 사용하면 ECU를 위한 최적의 기반을 만들고 관련 툴로 수반되는 모든 개발 작업을 간소화할 수 있습니다. MICROSAR 내장 소프트웨어는 AUTOSAR 클래식 및 적응형과 같은 관련 표준에 따라 개발되었습니다. 이 소프트웨어는 ISO 26262까지 ASIL D에 따른 안전 관련 애플리케이션에도 적합합니다. 또한, 지능형 사이버 보안 기능은 무단 액세스 (...)
발송: Vector Informatik GmbH
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시뮬레이션 모델

DRA75x and DRA74x BSDL Model

SPRM667.ZIP (14 KB) - BSDL Model
다운로드
시뮬레이션 모델

DRA75x and DRA74x IBIS Model

SPRM668.ZIP (18366 KB) - IBIS Model
다운로드
시뮬레이션 모델

DRA75x and DRA74x Thermal Model

SPRM669.ZIP (2 KB) - Thermal Model
다운로드
계산 툴

CLOCKTREETOOL — Sitara, 오토모티브, 비전 분석 및 디지털 신호 프로세서용 클록 트리 툴

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
사용 설명서: PDF
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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (ABC) 760 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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