DS90UB926Q-Q1
- AEC-Q100 Qualified for Automotive Applications
- Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
- Device HBM ESD Classification Level 3B
- Device CDM ESD Classification Level C6
- Device MM ESD Classification Level M3
- Bidirectional Control Interface Channel Interface With I2C-Compatible Serial Control Bus
- Supports High-Definition (720p) Digital Video Format
- RGB888 + VS, HS, DE and Synchronized I2S Audio Supported
- 5- to 85-MHz PCLK Supported
- Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
- AC-Coupled STP Interconnect up to 10 Meters
- Parallel LVCMOS Video Outputs
- I2C-Compatible Serial Control Bus for Configuration
- DC-Balanced and Scrambled Data With Embedded Clock
- Adaptive Cable Equalization
- Supports Repeater Application
- @ SPEED Link BIST Mode and LOCK Status Pin
- Image Enhancement (White Balance and Dithering) and Internal Pattern Generation
- EMI Minimization (SSCG and EPTO)
- Low Power Modes Minimize Power Dissipation
- Backward-Compatible With FPD-Link II
The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.
The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel datasheet (Rev. D) | PDF | HTML | 2017. 8. 3 | |
| 애플리케이션 노트 | Enabling GPIOs in DS90UB925 and DS90UB926 | 2015. 11. 10 | |||
| 애플리케이션 노트 | Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices | 2013. 5. 4 | |||
| 애플리케이션 노트 | I2C Communication Over FPD-Link III with Bidirectional Control Channel (Rev. A) | 2013. 4. 26 | |||
| 사용 설명서 | DS90UB926QSEVB User's Guide | 2012. 9. 20 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS90UB926QSEVB — DS90UB926Q 평가 모듈
The DS90UB926QSEVB is an evaluation board designed to demonstrate the performance and unique features of the DS90UB926Q FPD-Link III deserializer.
The DS90UB926QSEVB board is designed to accept any of TI’s compatible FPD-Link III serializer devices. The FPD-Link III serial input interface is (...)
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (NKB) | 60 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.