인터페이스 직렬 디지털 인터페이스(SDI) IC

LMH0341

활성

루프스루 및 LVDS 인터페이스를 지원하는 3G HD/SD DVB-ASI SDI 디시리얼라이저

제품 상세 정보

Function Deserializer Power consumption (mW) 520 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
Function Deserializer Power consumption (mW) 520 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • 5-Bit LVDS Interface
  • No External VCO or Clock Required
  • Reclocked Serial Loopthrough With Cable Driver
  • Powerdown Mode
  • 3.3V SMBus Configuration Interface
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to +85°C

Key Specifications

  • Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
  • Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
  • 0.6 UI Minimum Input Jitter Tolerance

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

  • 5-Bit LVDS Interface
  • No External VCO or Clock Required
  • Reclocked Serial Loopthrough With Cable Driver
  • Powerdown Mode
  • 3.3V SMBus Configuration Interface
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to +85°C

Key Specifications

  • Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
  • Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
  • 0.6 UI Minimum Input Jitter Tolerance

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.

The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.

The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.

The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.

The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.

The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.

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기술 자료

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12개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F datasheet (Rev. Q) 2013. 4. 16
선택 가이드 Broadcast and Professional Video Interface Solutions (Rev. E) PDF | HTML 2017. 4. 5
애플리케이션 노트 AN-1972 Board Layout Challenges in Serial Digital Interface (Rev. C) 2013. 4. 26
애플리케이션 노트 AN-2145 Power Considerations for SDI Products (Rev. B) 2013. 4. 26
애플리케이션 노트 AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013. 4. 26
애플리케이션 노트 AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 2013. 4. 26
애플리케이션 노트 Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 2013. 4. 26
애플리케이션 노트 AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) 2013. 4. 26
애플리케이션 노트 High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 2009. 11. 12
애플리케이션 노트 DS25CP104 in 3G SDI Router Application 2008. 8. 20
애플리케이션 노트 A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video 2008. 3. 18
설계 가이드 Broadcast Video Owner's Manual 2006. 11. 17

설계 및 개발

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코드 예제 또는 데모

BROADCAST_VIDEO_SERDES_IP — LVDS 인터페이스 SDI 시리얼라이저/디시리얼라이저에 대한 방송용 비디오 지원 코드

We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)

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