홈 전원 관리 멀티 채널 IC(PMIC)
홈
전원 관리
멀티 채널 IC(PMIC)

LP2998

활성

1.5A DDR 터미네이션 레귤레이터(셧다운 핀 포함)

지금 주문
데이터시트

LP2998

활성
데이터시트 지금 주문

제품 상세 정보

Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
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기술 문서

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모두 보기11
유형 직함 날짜
* Data sheet LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) PDF | HTML 2014/08/20
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09
Application note Limiting DDR Termination Regulators’ Inrush Current 2016/08/23
EVM User's guide AN-1813 LP2998 Evaluation Board (Rev. A) 2013/05/07
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 2013/05/06
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010/04/28
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010/04/20
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010/03/31
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010/03/26
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010/03/26
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010/03/26

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LP2998EVAL — LP2998용 평가 보드

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
시뮬레이션 모델

LP2998 PSPICE Transient Model (Rev. B)

SNVM695B.ZIP (48 KB) - PSpice Model
다운로드
시뮬레이션 모델

LP2998 TINA-TI Transient Reference Design

SNVMB49.TSC (599 KB) - TINA-TI Reference Design
다운로드
시뮬레이션 모델

LP2998 TINA-TI Transient Spice Model

SNVMB48.ZIP (39 KB) - TINA-TI Spice Model
다운로드
시뮬레이션 모델

LP2998 Unencrypted PSpice Model

SNVMAF5.ZIP (7 KB) - PSpice Model
다운로드
레퍼런스 디자인

TIDA-010011 — 보호 릴레이 프로세서 모듈을 위한 고효율 전원 공급 장치 아키텍처 레퍼런스 설계

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

PMP10600 — Xilinx® Zynq® 7000 시리즈(XC7Z015) 전원 솔루션, 5W - 레퍼런스 디자인

The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator.  It also features one LM3880 for power up and power (...)
Test report: PDF
회로도: PDF
레퍼런스 디자인

PMP10601 — Xilinx® Zynq® 7000 시리즈(XC7Z015) 전원 솔루션, 8W - 레퍼런스 디자인

The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also (...)
Test report: PDF
회로도: PDF
레퍼런스 디자인

PMP10613 — Xilinx Zynq 7000 시리즈(XC7Z045) 20W 레퍼런스 디자인

The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It (...)
Test report: PDF
회로도: PDF
레퍼런스 디자인

PMP9766 — 액티브 셀 밸런싱을 사용하는 슈퍼 커패시터 백업 전원 공급 장치 레퍼런스 디자인

This reference design describes a backup power circuit which addresses instantaneous protection against power interruptions by using a buck-boost converter and two stacked supercapacitors. The implementation is based on a completely integrated TPS63020 buck-boost converter circuit enabling a small (...)
Test report: PDF
회로도: PDF
레퍼런스 디자인

PMP10630 — 자일링스 킨텍스 울트라스케일(Kintex UltraScale) XCKU040 FPGA 전원 솔루션, 6W 레퍼런스 디자인

The PMP10630 reference design is a complete high density power solution for Xilinx® Kintex® UltraScale™ XCKU040 FPGA. This design uses an optimal combination of SIMPLE SWITCHER® modules and LDOs to provide all the necessary voltage rails in a small solution size of 36 x 43 mm (1.4 (...)
Test report: PDF
회로도: PDF
패키지 핀 다운로드
HSOIC (DDA) 8 옵션 보기
SOIC (D) 8 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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포럼 주제 모두 보기(영문)

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