SN54AHCT74

Name: SN54AHCT74
Brand: TI
SKU: SN54AHCT74
Price: 19.36 USD

활성

클리어 및 프리셋을 지원하는 듀얼 양극 에지 트리거 D형 플립플롭

지금 주문

데이터 시트

document-pdfAcrobat SNxAHCT74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. R) (영어) PDF | HTML

SN54AHCT74

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

2

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

70

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

20

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

2

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

70

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

20

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

14

130.4652 mm² 19.56 x 6.67

CFP (W)

14

58.023 mm² 9.21 x 6.3

LCCC (FK)

20

79.0321 mm² 8.89 x 8.89

Operating range of 4.5 V to 5.5 V
Low power consumption, 10-µA maximum I CC
±8-mA output drive at 5 V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250 mA per JESD 17

Operating range of 4.5 V to 5.5 V
Low power consumption, 10-µA maximum I CC
±8-mA output drive at 5 V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250 mA per JESD 17

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

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