제품 상세 정보

Technology family LS Number of channels 2 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 10000
Technology family LS Number of channels 2 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 10000
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73
  • Applications:
    • Dual 2-to 4-Line Decoder
    • Dual 1-to 4-Line Demultiplexer
    • 3-to 8-Line Decoder
    • 1-to 8-Line Demultiplexer
  • Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words
  • Input Clamping Diodes Simplify System Design
  • Choice of Outputs:
    • Totem Pole ('155, 'LS155A)
    • Open-Collector ('156, 'LS156)

 

  • Applications:
    • Dual 2-to 4-Line Decoder
    • Dual 1-to 4-Line Demultiplexer
    • 3-to 8-Line Decoder
    • 1-to 8-Line Demultiplexer
  • Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words
  • Input Clamping Diodes Simplify System Design
  • Choice of Outputs:
    • Totem Pole ('155, 'LS155A)
    • Open-Collector ('156, 'LS156)

 

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.

 

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.

 

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기술 자료

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11개 모두 보기
유형 직함 날짜
* Data sheet Dual 2-Line To 4-Line Decoders/Demultiplexers datasheet 1988/03/01
* SMD SN54LS155A SMD 5962-97508 2016/06/21
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Designing with the SN54/74LS123 (Rev. A) 1997/03/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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