SN54SC8T164-SEP
- Vendor item drawing available, VID V62/25620-01XE
- Radiation - Total Ionizing Dose (TID):
- TID characterized up to 50krad(Si)
- TID performance assurance up to 30krad(Si)
- Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30krad(Si)
- Radiation - Single-Event Effects (SEE):
- Single Event Latch-Up (SEL) immune up to 50MeV-cm2/mg at 125°C
- Single Event Transient (SET) characterized up to LET = 50MeV-cm2/mg
-
Wide operating range of 1.2V to 5.5V
-
Single-supply voltage translator:
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Up translation:
-
1.2V to 1.8V
-
1.5V to 2.5V
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1.8V to 3.3V
-
3.3V to 5.0V
-
-
Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
-
- 5.5V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5V or 3.3V VCC
- Latch-up performance exceeds 250mA per JESD 17
- Space enhanced plastic:
- Supports defense and aerospace applications
- Controlled baseline
- Au bondwire and NiPdAu lead finish
- Meets NASA ASTM E595 outgassing specification
- One fabrication, assembly, and test site
- Extended product life cycle
- Product traceability
The SN54SC8T164-SEP device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN54SC8T164-SEP Radiation Tolerant, 8-Bit Parallel-Out Serial Shift Registers datasheet | PDF | HTML | 2025/01/20 |
| * | Radiation & reliability report | SN54SC8T595-SEP Single-Event Effects (SEE) Radiation Report (Rev. A) | PDF | HTML | 2025/03/05 |
| * | Radiation & reliability report | SN54SC8T164-SEP Production Flow and Reliability Report | PDF | HTML | 2025/02/20 |
| * | Radiation & reliability report | SN54SC8T164-SEP Total Ionizing Dose (TID) Report | 2025/02/18 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈
14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 장치를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치