SN74ACT1284

활성

3상 출력을 지원하는 7비트 버스 인터페이스

제품 상세 정보

Technology family ACT Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family ACT Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 20 ns at 5 V
  • 3-State Outputs Directly Drive Bus Lines
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications

  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 20 ns at 5 V
  • 3-State Outputs Directly Drive Bus Lines
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
TXS0108E 활성 오픈 드레인 및 푸시-풀 애플리케이션을 위한 8비트 양방향 전압 레벨 시프터 Higher voltage range with open drain output

기술 자료

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유형 직함 날짜
* Data sheet SN54ACT1284, SN74ACT1284 datasheet (Rev. D) 2003/10/23

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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