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Technology family ACT Rating Military Operating temperature range (°C) -40 to 85
Technology family ACT Rating Military Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Dual Independent FIFOs Organized as:
  • 64 Words by 1 Bit Each - SN74ACT2226
  • 256 Words by 1 Bit Each - SN74ACT2228
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO
  • Input-Ready Flags Synchronized to Write Clocks
  • Output-Ready Flags Synchronized to Read Clocks
  • Half-Full and Almost-Full/Almost-Empty Flags
  • Support Clock Frequencies up to 22 MHz
  • Access Times of 20 ns
  • Low-Power Advanced CMOS Technology
  • Packaged in 24-Pin Small-Outline Integrated-Circuit Package
  • Dual Independent FIFOs Organized as:
  • 64 Words by 1 Bit Each - SN74ACT2226
  • 256 Words by 1 Bit Each - SN74ACT2228
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO
  • Input-Ready Flags Synchronized to Write Clocks
  • Output-Ready Flags Synchronized to Read Clocks
  • Half-Full and Almost-Full/Almost-Empty Flags
  • Support Clock Frequencies up to 22 MHz
  • Access Times of 20 ns
  • Low-Power Advanced CMOS Technology
  • Packaged in 24-Pin Small-Outline Integrated-Circuit Package

The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).

Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another.

Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously.

A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO.

The SN74ACT2226 and SN74ACT2228 are characterized for operation from -40°C to 85°C.

For more information on this device family, see the application report FIFOs With a Word Width of One Bit (literature number SCAA006).

The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).

Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another.

Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously.

A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO.

The SN74ACT2226 and SN74ACT2228 are characterized for operation from -40°C to 85°C.

For more information on this device family, see the application report FIFOs With a Word Width of One Bit (literature number SCAA006).

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모두 보기13
유형 직함 날짜
* Data sheet Dual 64 X 1, Dual 256 X 1 Clocked First-In, First-Out Memories datasheet (Rev. C) 1997/10/01
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01
Application note FIFOs With A Word Width Of One Bit (Rev. A) 1996/03/01
Application note Power-Dissipation Calculations for TI FIFO Products (Rev. A) 1996/03/01

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SOIC (DW) 24 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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