SN74ACT373-EP
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of –55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- 4.5-V to 5.5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 10 ns at 5 V
- Inputs Are TTL-Voltage Compatible
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN74ACT373-EP datasheet | 2003/09/30 | |
| * | VID | SN74ACT373-EP VID V6204619 | 2016/06/21 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004/06/22 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997/06/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996/04/01 |
설계 및 개발
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주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치