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Technology family ALVC Rating Military Operating temperature range (°C) to
Technology family ALVC Rating Military Operating temperature range (°C) to
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Operates at 3-V to 3.6-V VCC
  • Load Clock and Unload Clock Can Be Asynchronous or Coincident
  • Low-Power Advanced CMOS Technology
  • Full, Empty, and Half-Full Flags
  • Programmable Almost-Full/Almost-Empty Flag
  • Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates From 0 to 40 MHz
  • 3-State Outputs
  • Pin Compatible With SN74ACT7804
  • Packaged in Shrink Small-Outline 300-mil Package (DL) Using 25-mil Center-to-Center Spacing
  • Operates at 3-V to 3.6-V VCC
  • Load Clock and Unload Clock Can Be Asynchronous or Coincident
  • Low-Power Advanced CMOS Technology
  • Full, Empty, and Half-Full Flags
  • Programmable Almost-Full/Almost-Empty Flag
  • Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates From 0 to 40 MHz
  • 3-State Outputs
  • Pin Compatible With SN74ACT7804
  • Packaged in Shrink Small-Outline 300-mil Package (DL) Using 25-mil Center-to-Center Spacing

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7804 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. The SN74ALVC7804 is designed for 3-V to 3.6-V VCC operation.

Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect.

Status of the FIFO memory is monitored by the full (), empty (), half-full (HF), and almost- full/almost-empty (AF/AE) flags. The output is low when the memory is full and high when the memory is not full. The output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable () is low. The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.

A low level on the reset () resets the internal stack pointers and sets high, AF/AE high, HF low, and low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up. The first word loaded into empty memory causes to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable () is high.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7804 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. The SN74ALVC7804 is designed for 3-V to 3.6-V VCC operation.

Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect.

Status of the FIFO memory is monitored by the full (), empty (), half-full (HF), and almost- full/almost-empty (AF/AE) flags. The output is low when the memory is full and high when the memory is not full. The output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable () is low. The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.

A low level on the reset () resets the internal stack pointers and sets high, AF/AE high, HF low, and low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up. The first word loaded into empty memory causes to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable () is high.

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기술 문서

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모두 보기19
유형 직함 날짜
* Data sheet 512 X 18 First-In, First-Out datasheet 1995/01/01
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002/08/01
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999/09/08
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998/08/03
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998/05/13
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01
Application note Power-Dissipation Calculations for TI FIFO Products (Rev. A) 1996/03/01

설계 및 개발

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패키지 다운로드
SSOP (DL) 56 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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