SN74LVC112A

Name: SN74LVC112A
Brand: TI
SKU: SN74LVC112A
Price: 0.396 USD

활성

클리어 및 프리셋을 지원하는 듀얼 음극 에지 트리거 J-K 플립플롭

지금 주문

데이터 시트

document-pdfAcrobat SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet (Rev. M) (영어) PDF | HTML

SN74LVC112A

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

Technology family

LVC

Supply voltage (min) (V)

Supply voltage (max) (V)

3.6

Input type

TTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

150

Supply current (max) (µA)

IOL (max) (mA)

IOH (max) (mA)

-24

Features

Balanced outputs, Clear, Negative edge triggered, Over-voltage tolerant inputs, Preset, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

Technology family

LVC

Supply voltage (min) (V)

Supply voltage (max) (V)

3.6

Input type

TTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

150

Supply current (max) (µA)

IOL (max) (mA)

IOH (max) (mA)

-24

Features

Balanced outputs, Clear, Negative edge triggered, Over-voltage tolerant inputs, Preset, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

59.4 mm² 9.9 x 6

79.56 mm² 10.2 x 7.8

48.36 mm² 6.2 x 7.8

32 mm² 5 x 6.4

23.04 mm² 3.6 x 6.4

Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 3000-V Human-Body Model
- 200-V Machine Model
- 1500-V Charged-Device Model

Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 3000-V Human-Body Model
- 200-V Machine Model
- 1500-V Charged-Device Model

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

filter

기타 JK 플립플롭 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품

CD74AC112

활성

설정 및 리셋을 지원하는 듀얼 음극 에지 트리거 J-K 플립플롭 Different voltage range (2V to 6V), longer average propagation delay (7ns)

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

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28개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet (Rev. M)	PDF \| HTML	2014/12/26
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022/12/15
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	User guide	Signal Switch Data Book (Rev. A)		2003/11/14
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		2003/11/06
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		2002/12/18
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002/05/22
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002/03/27
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997/12/01
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997/08/01
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	LVC Characterization Information		1996/12/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits		1996/10/01
	Application note	Live Insertion		1996/10/01
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		1996/09/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01