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스위치 및 멀티플렉서
디지털 디멀티플렉서 및 디코더

SN74LVC1G18

활성

3상 비선택 출력을 지원하는 두 비인버팅 디멀티플렉서 중 하나

지금 주문
데이터 시트

SN74LVC1G18

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Catalog Supply current (max) (µA) 10
Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Catalog Supply current (max) (µA) 10
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Operating temperature from –40°C to +125°C
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Supports down translation to VCC
  • Max tpd of 3.4 ns at 3.3 V
  • Low power consumption, 10-µA max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA
    Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V Charged-device model (C101)
  • Operating temperature from –40°C to +125°C
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Supports down translation to VCC
  • Max tpd of 3.4 ns at 3.3 V
  • Low power consumption, 10-µA max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA
    Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V Charged-device model (C101)

This non-inverting demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G18 device is a 1-of-2 non-inverting demultiplexer with a 3-state output. This device buffers the data on input A and passes it to either output Y0 or Y1, depending on whether the state of the select (S) input is low or high, respectively.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This non-inverting demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G18 device is a 1-of-2 non-inverting demultiplexer with a 3-state output. This device buffers the data on input A and passes it to either output Y0 or Y1, depending on whether the state of the select (S) input is low or high, respectively.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74AUC1G19 활성 1/2 디코더/디멀티플렉서 Smaller voltage range (0.8V to 2.7V), shorter average propagation delay (1.7ns)
비교 대상 장치와 유사한 기능
SN74LVC1G19 활성 1/2 디코더/디멀티플렉서 Voltage range (1.65V to 5.5V), average drive strength (24mA), average propagation delay (5.5ns)

기술 자료

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27개 모두 보기
유형 직함 날짜
* Data sheet SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output datasheet (Rev. L) PDF | HTML 2019/08/19
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01
Selection guide Logic Guide (Rev. AC) PDF | HTML 1994/06/01

설계 및 개발

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평가 보드

5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈

5~8핀 수의 DCK, DCT, DCU, DRL 또는 DBV 패키지가 있는 모든 디바이스를 지원하도록 설계된 유연한 EVM.
사용 설명서: PDF
TI.com에서 구매 불가
평가 보드

5-8-NL-LOGIC-EVM — 5-8핀 DPW, DQE, DRY, DSF, DTM, DTQ 및 DTT 패키지를 지원하는 일반 로직 및 변환 EVM

DTT, DRY, DPW, DTM, DQE, DQM, DSF 또는 DTQ 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 일반 EVM. 보드 설계는 유연한 평가가 가능합니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
DSBGA (YZP) 6 Ultra Librarian
SOT-23 (DBV) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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