THS7347
- 3-Video Amplifiers for CVBS, S-Video, EDTV, HDTV Y'P'BP'R, G'B'R', and R'G'B' Video
- H/V Sync Paths with Adjustable Schmitt Trigger
- 2:1 Input Mux
- I2C Control of All Functions on Each Channel
- Unity-Gain Buffer Path for ADC Buffering:
- 500-MHz Bandwidth, 1200-V/µs Slew Rate
- Monitor Pass-Through Function:
- 500-MHz Bandwidth, 1300-V/µs Slew Rate
- 6-dB Gain with SAG Correction Capable
- High Output Impedance in Disable State
- Selectable Input Bias Modes:
- AC-Coupled with Sync-Tip Clamp
- AC-Coupled with Bias
- DC-Coupled with Offset Shift
- DC-Coupled
- +2.7-V to +5-V Single-Supply Operation
- Total Power Consumption: 265 mW at 3.3 V
- Disable Function Reduces Current to 0.1 µA
- Rail-to-Rail Output:
- Output Swings Within 0.1 V of the Rails, Allowing AC- or DC-Output Coupling
- Lead-free, RoHS TQFP Package
Fabricated using the revolutionary complimentary silicon-germanium (SiGe) BiCom3 process, the THS7347 is a low-power, single-supply 2.7-V to 5-V 3-channel integrated video buffer with horizontal (H) and vertical (V) sync signal paths. It incorporates a 500-MHz bandwidth, 1200-V/µs unity-gain buffer ideal for driving analog-to-digital converters (ADCs) and video decoders. In parallel with the unity-gain buffer, a monitor pass-through path allows for passing the input signal on to other systems. This path has a 6-dB gain, 500-MHz bandwidth, 1300-V/µs slew rate, SAG correction capability, and high output impedance while disabled.
Each channel of the THS7347 is individually I2C-configurable for all functions, including controlling the 2:1 input mux. Its rail-to-rail output stage allows for both ac- and dc-coupling applications.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | 3-Ch RGBHV Video Buffer w/ I²C Ctrl, 2:1 Input MUX, Monitor Pass-Through datasheet (Rev. B) | 2011. 10. 10 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTQFP (PHP) | 48 | Ultra Librarian |