홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

TMS320C40

새 설계에 권장하지 않음

디지털 신호 프로세서

지금 주문
데이터시트
TMS320C40은(는) 새 설계에 권장하지 않습니다
이 제품은 이전 설계를 지원하기 위해 계속 생산 중이지만 새로운 설계에 사용하는 것은 권장하지 않습니다. 다음 대안 중 하나를 고려하십시오.
open-in-new 대안 비교
비교 대상 장치와 유사한 기능
TMS320C6747 활성 저전력 C674x 부동 소수점 DSP - 456MHz, PBGA This product is a newer generation of floating point DSPs with higher performance & improved connectivity options.

TMS320C40

새 설계에 권장하지 않음
데이터시트 지금 주문

제품 상세 정보

DSP (max) (MHz) 50, 60 Rating Military Operating temperature range (°C) to
DSP (max) (MHz) 50, 60 Rating Military Operating temperature range (°C) to
CPGA (GF) 325 2232.5625 mm² 47.25 x 47.25
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • '320C40-60:
      33-ns Instruction Cycle Time,
      330 MOPS, 60 MFLOPS,
      30 MIPS, 384M Bytes/s
    • '320C40-50:
      40-ns Instruction Cycle Time
    • '320C40-40:
      50-ns Instruction Cycle Time
  • Six Communications Ports
  • Six-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
  • Single Cycle, 1/x, 1/
  • Source-Code Compatible With TMS320C3x
  • Single-Cycle 40-Bit Floating-Point,
    32-Bit Integer Multipliers
  • Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
  • IEEE 1149.1 (JTAG) Boundary Scan Compatible
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-Bus, Data-Bus, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • 325-Pin Ceramic Grid Array (GF Suffix)
  • Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
  • Software-Communication-Port Reset
  • NMI\ With Bus-Grant Feature
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
  • IDLE2 Clock-Stop Power-Down Mode
  • 5-V Operation

    IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture
    EPIC and TI are trademarks of Texas Instruments Incorporated.
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • '320C40-60:
      33-ns Instruction Cycle Time,
      330 MOPS, 60 MFLOPS,
      30 MIPS, 384M Bytes/s
    • '320C40-50:
      40-ns Instruction Cycle Time
    • '320C40-40:
      50-ns Instruction Cycle Time
  • Six Communications Ports
  • Six-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
  • Single Cycle, 1/x, 1/
  • Source-Code Compatible With TMS320C3x
  • Single-Cycle 40-Bit Floating-Point,
    32-Bit Integer Multipliers
  • Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
  • IEEE 1149.1 (JTAG) Boundary Scan Compatible
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-Bus, Data-Bus, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • 325-Pin Ceramic Grid Array (GF Suffix)
  • Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
  • Software-Communication-Port Reset
  • NMI\ With Bus-Grant Feature
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
  • IDLE2 Clock-Stop Power-Down Mode
  • 5-V Operation

    IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture
    EPIC and TI are trademarks of Texas Instruments Incorporated.

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.
open-in-new 기타 DSP(디지털 신호 프로세서) 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기33
유형 직함 날짜
* Data sheet Digital Signal Processor datasheet 1996/01/01
Application note 320C3x, 320C4x, and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D) 2004/08/06
User guide TMS320C3x/C4x Assembly Language Tools User's Guide (Rev. D) 1998/04/16
User guide TMS320C3x/C4x Optimizing C Compiler User's Guide (Rev. H) 1998/04/14
Application note Implementing Continuously Programmable Digital Filters w/ TMS320C30/40 DSP (Rev. A) 1997/08/01
Application note Predator: A Posture Tracking System 1997/08/01
Application note A Hardware Monitor Using TMS320C40 Analysis Module & JTAG for Perf Measurements 1997/07/01
Application note Creating an Interactive Simulation Environment Using TMS320C40 Multi-DSP System 1997/07/01
Application note Digital Monopulse Doppler Radar and DSP Teaching 1997/07/01
Application note EDRAM Controller for the 60MHz TMS320C40 DSP 1997/07/01
Application note Implementing a Digital Tracker for Monopulse Radar Using the TMS320C40 DSP 1997/07/01
Application note Implementing a Real-Time Application on a TMS320C40 Multi-DSP 1997/07/01
Application note A Novel Way of Using TMS320C40 Cache 1997/06/01
Application note A Simple Way to Terminate Unused TMS320C40 Comm Ports 1997/06/01
Application note Designing With TMS320C40 Comm Ports: Part 1 1997/06/01
Application note Fast Logarithms on a Floating-Point Device 1997/06/01
Application note TMS320C40 Boot Loader Selection 1997/06/01
Application note TMS320C40 DMA Memory Transfer Timing 1997/06/01
Application note TMS320C40 Emulator TIPs 1997/06/01
Application note Video Restoration on a Multiple TMS320C40 System 1996/11/01
Application note Design of Active Noise Control Systems With the TMS320 Family 1996/06/01
User guide JTAG/MPSD Emulation Technical Reference (Rev. A) 1994/12/01
Application note Setting Up TMS320 DSP Interrupts in 'C' 1994/11/01
User guide TMS320C4x Parallel Runtime Support Library User's Guide (Rev. A) 1994/10/01
User guide TMS320C4x Parallel Processing Development System Technical Reference (Rev. A) 1994/04/08
Application note Parallel 2-D FFT Implementation With TMS320C4x DSPs (Rev. A) 1994/02/01
Application note Parallel Digital Signal Processing With the TMS320C40 1994/02/01
Application note Parallel Processing With TMS320C4x 1994/02/01
Application note Prototyping the TI TMS320C40 to the Cypress VIC068/VAC068 VME Interface 1994/02/01
Application note Transmission of Still and Moving Images Over Narrowband Channels 1994/02/01
Application note Calculation of TMS320C40 Power Dissipation 1993/11/01
User guide Parallel Debug Mgr Addendum to TMS320C4x & TMS320C5x C Source Debugger UGs 1993/04/01
User guide TMS320C4x C Source Debugger User's Guide 1992/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

지원 소프트웨어

TMDS3240130SP2 — Download TMS320C3x/C4x Code Composer v4.1 Service Pack 2

Additional Information


Code Composer v4 was the last release of the Code Composer IDE that supported older digital signal processors such as TMS320C3x/4x and TMS320C2x/C5x.  There were different versions for these families. These products are no longer available for purchase or download. (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
TMS320C40 — 디지털 신호 프로세서
다운로드
시뮬레이션 모델

C40 GFL BSDL Model

SPRM168.ZIP (6 KB) - BSDL Model
다운로드
설계 툴

PROCESSORS-3P-SEARCH — Arm 기반 MPU, arm 기반 MCU 및 DSP 타사 검색 툴

TI는 여러 회사와의 협력을 통해 TI 프로세서를 사용하여 광범위한 소프트웨어, 툴 및 SOM을 제공해서 생산 단계로 가는 속도를 높이고 있습니다. 이 검색 툴을 다운로드하여 타사 솔루션을 빠르게 검색하고 필요에 맞는 올바른 타사를 찾아보세요. 여기에 나열된 소프트웨어, 툴 및 모듈은 텍사스 인스트루먼트가 아닌 독립적인 타사에서 생산 및 관리하고 있습니다.

검색 툴은 다음과 같이 제품 유형별로 분류되어 있습니다.

  • 툴에는 IDE/컴파일러, 디버그 및 추적, 시뮬레이션 및 모델링 소프트웨어, 플래시 프로그래머가 포함되어 있습니다.
  • OS에는 (...)
다운로드
패키지 핀 다운로드
CPGA (GF) 325 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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