These synchronous 4-bit up/down binary presettable counters
feature an internal carry look-ahead circuitry for cascading in
high-speed counting applications. Synchronous operation is provided
by having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by the
count-enable (
, 
) inputs and internal gating. This
mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they may be preset to either level. The load-input circuitry allows loading with the carry-enable output of cascaded counters. Because loading is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The internal carry look-ahead circuitry provides for cascading
counters for n-bit synchronous application without additional gating.
and inputs and a ripple-carry output
(
) are
instrumental in accomplishing this function. Both and must be low to count. The
direction of the count is determined by the level of the up/down
(U/D\) input. When U/D\ is high, the counter counts up; when low, it
counts down. is fed forward
to enable . , thus enabled, produces a
low-level pulse while the count is zero (all inputs low) counting
down or maximum (15) counting up. This low-level overflow
ripple-carry pulse can be used to enable successive cascaded stages.
Transitions at or are allowed regardless of the
level of the clock input. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes
at control inputs (,
, 
, or U/D\) that modify the
operating mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) is dictated solely by the conditions
meeting the stable setup and hold times.
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Synchronous 4-Bit Up/Down Binary Counters datasheet (Rev. B) | 01 Dec 1994 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 Aug 1995 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SOIC (D) | 16 | View options |
| SOP (NS) | 16 | View options |
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