ADC12D1000RF
- Excellent Noise and Linearity up to and Above fIN =
2.7 GHz - Configurable to Either 3.2 or 2 GSPS Interleaved
or 1600 or 1000 MSPS Dual ADC - New DESCLKIQ Mode for High Bandwidth, High
Sampling Rate Apps - Pin-Compatible With ADC10D1x00, ADC12D1x00
- AutoSync Feature for Multi-Chip Synchronization
- Internally Terminated, Buffered, Differential Analog
Inputs - Interleaved Timing Automatic and Manual Skew
Adjust - Test Patterns at Output for System Debug
- Time Stamp Feature to Capture External Trigger
- Programmable Gain, Offset, and tAD Adjust
Feature - 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
- Key Specifications
- Resolution 12 Bits
- Interleaved 3.2- and 2-GSPS ADC
- IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
dBFS (Typical) - IMD3 (Fin = 2.7 GHz at –16 dBFS) –66.7/–85
dBFS (Typical) - Noise Floor –154.6/–154 dBm/Hz (Typical)
- Power 3.94/3.42 W (Typical)
- IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
- Dual 1600/1000 MSPS ADC, Fin = 498 MHz
- ENOB 9.2/9.4 Bits (Typical)
- SNR 58.2/58.8 dB (Typical)
- SFDR 66.7/71.9 dBc (Typical)
- Power per Channel 1.97/1.71 W (Typical)
The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone
The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC12D1x00RF 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC datasheet (Rev. H) | PDF | HTML | 2015/8/31 | ||
| 應用說明 | AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) | 2017/2/3 | ||||
| 應用說明 | Signal Chain Noise Figure Analysis | 2014/10/29 | ||||
| 應用說明 | Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat | 2013/12/9 | ||||
| 應用說明 | AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) | 2013/5/1 | ||||
| 使用指南 | Schematic and Layout Recommendations for the GSPS ADC | 2013/4/29 | ||||
| 應用說明 | AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) | 2013/4/26 | ||||
| 應用說明 | From Sample Instant to Data Output: Understanding Latency in the GSPS ADC | 2012/12/18 | ||||
| Product overview | ADC12Dxx00RF Direct RF-Sampling ADC Family | 2012/5/16 |
設計與開發
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WAVEVISION5 — WaveVision 5 Software
WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.
While WaveVision 5 software (...)
TIDA-00113 — 以單通道或雙通道模式驅動 GSPS ADC，適用於高頻寬應用
This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications. The tradeoffs considered include balun construction, insertion loss, dynamic (...)
TIDA-00479 — 適用於 GSPS ADC 的最佳時鐘來源參考設計
ADC12D1600RFRB 參考設計提供了一個平台，用於展示包含時脈、電源管理和訊號處理的高速數位器應用。此參考設計採用 1.6 GSPS ADC12D1600RF 裝置、板載 FPGA Xilinx Virtex 4 和高效能時脈合成器 LMX2531，以滿足 9 位元 ENOB 高速數位器的系統需求。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PBGA (NXA) | 292 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。