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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12D1600QML-SP

現行

Radiation-hardened, 300krad, 12 bit, dual 1.6GSPS or single 3.2GSPS ADC

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產品規格表

ADC12D1600QML-SP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA (NAA) 376 780.6436 mm² (0 mm × 0 mm)
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC12D1600QML 12-Bit, 3.2/2.0 GSPS RF Sampling ADC datasheet 2012/12/17
* 輻射及可靠性報告 ADC12D1600QML-SP/ADC12D1620QML-SP Single-Event Effects (SEE) Radiation Report 2020/7/27
* 輻射及可靠性報告 Single Event Effects Characterization of Texas Instruments ADC12D1600CCMLS 2018/6/14
* 輻射及可靠性報告 ADC12D1600CCMLS TID Report 2013/1/17
* 輻射及可靠性報告 Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012/5/4
選擇指南 TI Space Products (Rev. L) 2026/3/27
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Application brief Understanding Op Amp Noise in Audio Circuits PDF | HTML 2021/6/14
應用說明 AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017/2/3
應用說明 Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 2015/12/7
應用說明 Signal Chain Noise Figure Analysis 2014/10/29
應用說明 Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 2014/8/6
應用說明 AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 2013/5/1
應用說明 From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012/12/18
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 2012/5/16

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模擬型號

ADC12D1600 IBIS Model (Rev. A)

SNAM125A.ZIP (43 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
CCGA (NAA) 376 Ultra Librarian
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