產品詳細資料

Sample rate (max) (Msps) 155 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1100 Features High Performance Rating Space Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 967 Architecture Pipeline SNR (dB) 70.1 ENOB (Bits) 11.3 SFDR (dB) 82.3 Operating temperature range (°C) -55 to 125 Input buffer No Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 155 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1100 Features High Performance Rating Space Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 967 Architecture Pipeline SNR (dB) 70.1 ENOB (Bits) 11.3 SFDR (dB) 82.3 Operating temperature range (°C) -55 to 125 Input buffer No Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
CFP (NBA) 48 132.25 mm² 11.5 x 11.5
  • 5962R0626201VXC
    • Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-up 120 MeV-cm2/mg
      (See Radiation Reports)
  • 1.1-GHz Full-Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Low-Power Consumption
  • Internal Precision 1-V Reference
  • Single-Ended or Differential Clock Modes
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Dual 3.3-V and 1.8-V Supply Operation (±10%)
  • Power-Down Mode
  • Offset Binary or 2’s Complement Output Data Format
  • 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-mm Pin-Pitch)
  • Key Specifications
    • Resolution 14 Bits
    • Conversion Rate 155 MSPS
    • SNR (fIN = 70 MHz) 70.1 dBFS (typ)
    • SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
    • ENOB (fIN = 70 MHz) 11.3 Bits (typ)
    • Full-Power Bandwidth 1.1 GHz (typ)
    • Power Consumption 967 mW (typ)
  • 5962R0626201VXC
    • Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-up 120 MeV-cm2/mg
      (See Radiation Reports)
  • 1.1-GHz Full-Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Low-Power Consumption
  • Internal Precision 1-V Reference
  • Single-Ended or Differential Clock Modes
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Dual 3.3-V and 1.8-V Supply Operation (±10%)
  • Power-Down Mode
  • Offset Binary or 2’s Complement Output Data Format
  • 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-mm Pin-Pitch)
  • Key Specifications
    • Resolution 14 Bits
    • Conversion Rate 155 MSPS
    • SNR (fIN = 70 MHz) 70.1 dBFS (typ)
    • SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
    • ENOB (fIN = 70 MHz) 11.3 Bits (typ)
    • Full-Power Bandwidth 1.1 GHz (typ)
    • Power Consumption 967 mW (typ)

The ADC14155QML-SP is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 MSPS. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes 967 mW of power at 155 MSPS.

The separate 1.8-V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The Clock mode (differential versus single-ended) and output data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155QML-SP is available in a 48-lead thermally enhanced multi-layer ceramic quad package and operates over the military temperature range of –55°C to +125°C.

The ADC14155QML-SP is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 MSPS. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes 967 mW of power at 155 MSPS.

The separate 1.8-V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The Clock mode (differential versus single-ended) and output data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155QML-SP is available in a 48-lead thermally enhanced multi-layer ceramic quad package and operates over the military temperature range of –55°C to +125°C.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 15
重要文件 類型 標題 格式選項 日期
* Data sheet ADC14155QML-SP, radiation hardened, 14-Bit, 155-MSPS, 1.1-GHz bandwidth A/D converter datasheet (Rev. L) PDF | HTML 2019年 2月 13日
* SMD ADC14155QML-SP SMD 5962-06262 2018年 5月 29日
* Radiation & reliability report ADC141555W-MLS, DAC121S101WGRQV, ADC08D1000WGFQV TID Report 2012年 5月 7日
* Radiation & reliability report ADC14155W-MLS SEL Report 2012年 5月 7日
* Radiation & reliability report ADC14155W-MLS SEU Report 2012年 5月 7日
* Radiation & reliability report ADC14155W-MLS TID Report 2012年 5月 7日
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
Selection guide TI Space Products (Rev. L) 2026年 3月 27日
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025年 6月 17日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025年 6月 10日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025年 2月 20日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
E-book Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
Application note AN-1718 Differential Amplifier Applications Up to 400 MHz (Rev. B) 2013年 5月 1日
User guide ADC14155: 14-Bit, 155 MSPS Analog to Digital Converter User Guide 2012年 2月 21日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

應用軟體及架構

WAVEVISION4 — 資料採集和分析軟體

WaveVision 4 software is part of the WaveVision system that includes the WaveVision Data Capture Board. The WaveVision system an easy-to-use data acquisition and analysis tool, designed to help you evaluate TI's analog-to-digital and digital-to-analog converter products. Used in conjunction with (...)
使用指南: PDF
模擬型號

ADC14155QML IBIS Model

SNAM017.ZIP (20 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
封裝 針腳 CAD 符號、佔位空間與 3D 模型
CFP (NBA) 48 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片