產品詳細資料

Sample rate (max) (Msps) 25 Resolution (bps) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features High Dynamic Range, High Performance, Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 177 Architecture Pipeline SNR (dB) 70.2 ENOB (bit) 11.5 SFDR (dB) 87 Operating temperature range (°C) -40 to 125 Input buffer Yes
Sample rate (max) (Msps) 25 Resolution (bps) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features High Dynamic Range, High Performance, Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 177 Architecture Pipeline SNR (dB) 70.2 ENOB (bit) 11.5 SFDR (dB) 87 Operating temperature range (°C) -40 to 125 Input buffer Yes
VQFNP (RWE) 56 64 mm² 8 x 8
  • AEC-Q100 Qualified for automotive applications
    • Temperature grade 1: –40°C to 125°C TA
  • Quad channel
  • 12-Bit resolution
  • Single supply: 1.8 V
  • Serial LVDS interface
  • Flexible input clock buffer with divide-by-1, -2, -4
  • SNR = 71.1 dBFS, SFDR = 90 dBc at
    fIN = 10 MHz
  • Ultra-low power consumption:
    • 44 mW/Ch at 25 MSPS
  • Channel isolation: 105 dB
  • Internal dither and chopper
  • Support for multichip synchronization
  • AEC-Q100 Qualified for automotive applications
    • Temperature grade 1: –40°C to 125°C TA
  • Quad channel
  • 12-Bit resolution
  • Single supply: 1.8 V
  • Serial LVDS interface
  • Flexible input clock buffer with divide-by-1, -2, -4
  • SNR = 71.1 dBFS, SFDR = 90 dBc at
    fIN = 10 MHz
  • Ultra-low power consumption:
    • 44 mW/Ch at 25 MSPS
  • Channel isolation: 105 dB
  • Internal dither and chopper
  • Support for multichip synchronization

The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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類型 標題 日期
* Data sheet ADC3421-Q1 Automotive, Quad-Channel, 12-Bit, 25-MSPS Analog-to-Digital Converter datasheet (Rev. A) PDF | HTML 2020年 3月 25日
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 2018年 8月 24日

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