產品詳細資料

Sample rate (max) (Msps) 50 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 228 Architecture Pipeline SNR (dB) 73.5 ENOB (bit) 11.9 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 50 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 228 Architecture Pipeline SNR (dB) 73.5 ENOB (bit) 11.9 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RTQ) 56 64 mm² 8 x 8
  • Quad Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer With Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible With 12-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)
  • Quad Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer With Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible With 12-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.

The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.

The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.

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* Data sheet ADC344x Quad-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. B) PDF | HTML 2017年 4月 17日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 2018年 8月 24日

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ADC3442EVM — ADC3442 四通道、14 位元、50 MSPS 類比轉數位轉換器評估模組

ADC3442EVM 評估模組展示低功耗四路 50Msps 14 位元 ADC 的性能。內含 ADC3442 裝置與 TI 電壓穩壓器,可提供必要的電壓。ADC 的輸入預設連接至變壓器輸入,可連接至 50 ohm 單端訊號來源。時鐘輸入是透過變壓器輸入來提供的,可連接至 50 ohm 單端時鐘來源。系統會提供 SYSREF 輸入,以允許完整的系統同步化。透過板載 USB 連接和 GUI 提供暫存器存取權。

使用指南: PDF
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模擬型號

ADC3444 IBIS Model

SLAM232.ZIP (36 KB) - IBIS Model
模擬型號

ADC3xxx Pspice Model

SLAM228.ZIP (15 KB) - PSpice Model
模擬型號

ADC3xxx TINA Model

SLAM226.ZIP (3 KB) - TINA-TI Spice Model
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ADC3xxx TINA Reference Design

SLAM227.TSC (1083 KB) - TINA-TI Reference Design
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RTQ) 56 Ultra Librarian

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