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The ADS5231 is a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter (ADC). This converter includes a high-bandwidth sample-and-hold amplifier that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of the sample-and-hold amplifier and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity.
The ADS5231 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled, allowing low-drive, external references to be used for improved tracking in multichannel systems.
The ADS5231 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testing on a printed circuit board (PCB).
The ADS5231 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS5231 is available in a TQFP-64 package.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | Dual, 12-Bit, 40MSPS, +3.3V Analog-to-Digital Converter datasheet (Rev. A) | 2007年 1月 16日 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 |
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ADS5231EVM 設計旨在提供易於評估具備 CMOS 輸出的雙 12 位元、40 MSPS ADS5231 類比轉數位轉換器的性能。ADS5231EVM 可配對 ADC 數位擷取卡 TSW1100，以快速評估裝置的效能。
The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.
Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Analog Engineer's Calc Installer
General calculator tool for analog design support.