CDC111
- Low-Output Skew for Clock-Distribution Applications
- Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
- Distributes Differential Clock Inputs to Nine Differential Clock Outputs
- Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
- Single-Ended LVPECL-Compatible Output Enable
- Packaged in Plastic Chip Carrier
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-
transmission lines.
When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).
The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
技術文件
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檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 1-Line To 9-Line Differential LVPECL Clock Driver datasheet (Rev. G) | 1999年 8月 28日 | |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007年 10月 17日 | ||
| Application note | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003年 2月 19日 |
設計與開發
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模擬工具
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| PLCC (FN) | 28 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點