CDCE62005
- Superior Performance:
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz - Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
- Flexible Frequency Planning:
- 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
- Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
- Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
- Output Frequency up to 1.5 GHz in Fan-Out Mode
- Independent Coarse Skew Control on all Outputs
- High Flexibility:
- Integrated EEPROM Determines Device Configuration at Power-up
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
- 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
- –40°C to +85°C Temperature Range
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).
The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet (Rev. G) | PDF | HTML | 2016/5/23 | ||
| 使用指南 | TSW6011EVM Quick Start Guide (Rev. D) | 2016/8/17 | ||||
| 應用說明 | Clocking Design Guidelines: Unused Pins | 2015/11/19 | ||||
| 應用說明 | Effects of Clock Spur on High Speed DAC Performance (Rev. A) | 2015/5/18 | ||||
| 應用說明 | Effects of Clock Noise on High Speed DAC Performance | 2012/11/8 | ||||
| 應用說明 | Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 | 2011/8/11 | ||||
| 應用說明 | CDCE62005 Application Report | 2008/11/21 | ||||
| 應用說明 | LAN & WAN clock generation and muxing using the CDCE62005 | 2008/11/19 | ||||
| 使用指南 | Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz | 2008/11/11 | ||||
| 應用說明 | CDCE62005 Phase Noise and Jitter Cleaning Performance | 2008/9/5 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
CDCE62005EVM — CDCE62005EVM 評估模組
DAC3152EVM — DAC3152 雙通道、10 位元、500-MSPS 數位轉類比轉換器評估模組
DAC3152EVM 是可讓設計人員用於評估德州儀器 (TI) 的雙通道 10 位元 500 MSPS DAC3152 數位轉類比轉換器 (DAC) 性能的電路板，其具備 10 位元組寬 DDR LVDS 資料輸入、極低功耗、尺寸和延遲。EVM 提供了可在不一定配備直接 RF TRF370333、350MHz 至 4.0GHz 正交調變器的情況下測試 DAC3152 的靈活環境，該調變器可將來自 DAC 的 I/Q 輸出升頻為射頻。
此 EVM 能與 TSW3100 模式產生器配合使用以執行廣泛的測試。TSW3100 產生測試模式，該模式將透過 LVDS 埠饋送至 (...)
DAC3162EVM — DAC3162 雙通道、12 位元、500-MSPS 數位轉類比轉換器評估模組
DAC3162EVM 是可讓設計人員用於評估德州儀器 (TI) 的雙通道 12 位元 500 MSPS DAC3162 數位轉類比轉換器 (DAC) 性能的電路板，其具備 12 位元組寬 DDR LVDS 資料輸入、極低功耗、尺寸和延遲。EVM 提供了可在不一定配備直接 RF TRF370333、350MHz 至 4.0GHz 正交調變器的情況下測試 DAC3162 的靈活環境，該調變器可將來自 DAC 的 I/Q 輸出升頻為射頻。
此 EVM 能與 TSW3100 模式產生器配合使用以執行廣泛的測試。TSW3100 產生測試模式，該模式將透過 LVDS 埠饋送至 (...)
DAC3283EVM — DAC3283 雙通道、16 位元、800-MSPS、1x-4x 內插數位轉類比評估模組
The DAC3283EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS DAC3283 digital-to-analog converter (DAC) with 8-byte wide DDR LVDS data input, integrated 2x/4x interpolation filters and exceptional linearity at high IFs. The (...)
ACROVIEW-3P-AP6000 — AP6000 programmer support all TI programmable chips, including EP Product, Power ICs, and Gauge ICs
AP6000, launched by Acroview, is a universal programmer designed to support TI ICs across all series. Leveraging Acroview's highly skilled algorithm R&D engineering team, it delivers the fastest chip support speed in the industry.The AP6000 is capable of programming 8 chips simultaneously, and (...)
ACROVIEW-3P-AP8000 — AP8000 Universal Programming System, including all TI programmable chips.
AP8000 is a leading technology platform of Universal Programming developed by Acroview. We have an accomplished team of algorithm R&D engineers, to offer the fastest chip support software development service among the industry. The AP8000 can support the programming of 8 chips simultaneously. (...)
TIDA-00078 — 具有 I/Q 校正的直接降壓轉換系統
在 TSW6011EVM 的現場可編程閘陣列 (FPGA) 中實作的 I/Q 修正區塊可幫助使用者在無線系統中採用直接降頻轉換接收器架構。I/Q 校正區塊包含單分接頭盲算法，可修正複數零 IF 接收器系統中的頻率無關 I/Q 不平衡。除了 I/Q 校正區塊，FPGA 還包括一個數位增益區塊、一個數位功率測量區塊、2 個內插區塊、一個 I/Q 偏移校正區塊和一個正交混合區塊。
TIDEP0036 — 使用 TMS320C6657 實作高效率 OPUS 轉碼器解決方案的參考設計
TIDEP0036 參考設計提供可在 TMS320C6657 裝置上輕鬆執行的 TI 最佳化 Opus 編碼器/解碼器範例。由於 Opus 支援多種位元率、訊框大小及取樣率（這些全都具有低延遲），因此適用於語音通訊、網路音訊，甚至高性能音訊處理應用。 此設計還特別強調在 DSP 上實作 Opus 編解碼器，相較於通用處理器（例如 ARM）所達成的效能提升。 根據在通用處理器上執行的代碼最佳化程度，在 C66x TI DSP 核心上實作 Opus 編解碼器的性能是實作 ARM CORTEX A-15 的 3 倍。TMS320C66x DSP 同時支援音訊和視訊編解碼器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。