LMK1D1208I

現行

具有 I²C 的 8 通道輸出、1.8-V、2.5-V 和 3.3-V LVDS 緩衝器

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產品規格表

document-pdfAcrobat LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer datasheet (Rev. A) (英文) PDF | HTML

LMK1D1208I

現行

立即訂購

產品詳細資料

Number of outputs

8

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

8

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

High-performance LVDS clock buffer family with 2 inputs and 8 outputs
Output frequency up to 2 GHz
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Device configurability through I 2C programming
- Individual input and output enable/disable
- Individual output amplitude select (standard or boosted)
- Bank input multiplexer
Four programmable I 2C addresses through IDX pins
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
Fail-safe inputs
LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available
- 6-mm × 6-mm, 40-Pin VQFN (RHA)

High-performance LVDS clock buffer family with 2 inputs and 8 outputs
Output frequency up to 2 GHz
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Device configurability through I 2C programming
- Individual input and output enable/disable
- Individual output amplitude select (standard or boosted)
- Bank input multiplexer
Four programmable I 2C addresses through IDX pins
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
Fail-safe inputs
LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available
- 6-mm × 6-mm, 40-Pin VQFN (RHA)

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2023/6/14

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開發板

LMK1D1208IEVM — 適用具 I²C 之 8 通道輸出、1.8-V、2.5-V 和 3.3-V LVDS 緩衝器的 LMK1D1208I 評估模組

LMK1D1208I 評估模組 (EVM) 旨在示範 LMK1D1208I 的電氣性能。LMK1D1208I 是具有兩個差分輸入和八個 LVDS 輸出的 I2C 可配置高性能、低附加抖動 LVDS 時脈緩衝器。LMK1D1208IEVM 配備 50-Ω SMA 連接器和阻抗控制的 50-Ω 微帶傳輸線，以提供最佳性能。

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