SN74AUP1T17
- Single-Supply Voltage Translator
- Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
- 2.5 V to 3.3 V (at VCC = 3.3 V)
- 1.8 V to 2.5 V (at VCC = 2.5 V)
- 3.3 V to 2.5 V (at VCC = 2.5 V
- Schmitt-Trigger Inputs Reject Input Noise and
Provide Better Output Signal Integrity - Ioff Supports Partial Power Down (VCC = 0 V)
- Very Low Static Power Consumption:
0.1 µA - Very Low Dynamic Power Consumption:
0.9 µA - Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - Pb-Free Packages Available: SC-70 (DCK)
2 × 2.1 × 0.65 mm (Height 1.1 mm) - More Gate Options Available at
www.ti.com/littlelogic - ESD Performance Tested Per JESD 22
- 2000-V Human Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human Body Model
- APPLICATIONS
- AV Receivers
- Audio Dock: Portable
- Blu-ray Players and Home Theaters
- MP3 Players and Recorders
- Personal Digital Assistant (PDA)
- Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital - Solid State Drive (SSD): Client and Enterprise
- TV: LCD/Digital and High-Definition (HDTV)
- Tablet: Enterprise
- Video Analytics: Servers
- Wireless Headsets, Keyboards, and Mice
All other trademarks are the property of their respective owners
The SN74AUP1T17 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industry–s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity.
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T17 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN74AUP1T17 Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, Single Schmitt-Trigger Buffer Gate datasheet (Rev. A) | PDF | HTML | 2015年 6月 30日 |
| Application brief | Understanding Schmitt Triggers (Rev. B) | PDF | HTML | 2025年 4月 17日 | |
| Application note | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024年 10月 2日 | |
| Application note | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024年 7月 12日 | |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
| Selection guide | Voltage Translation Buying Guide (Rev. A) | 2021年 4月 15日 |
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
TIDA-00268 — Thunderbolt™ 單連接埠週邊設備參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點