產品詳細資料

Technology family AVC Bits (#) 16 High input voltage (min) (V) 0.91 High input voltage (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 80 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 16 High input voltage (min) (V) 0.91 High input voltage (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 80 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • Dynamic Output Control (DOC™) Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Control Inputs VIH/VIL Levels are Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power Supply Range
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus, DOC are trademarks of Texas Instruments.

  • Member of the Texas Instruments Widebus™ Family
  • Dynamic Output Control (DOC™) Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Control Inputs VIH/VIL Levels are Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power Supply Range
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus, DOC are trademarks of Texas Instruments.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCBH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCBH164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB .

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCBH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCBH164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB .

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.

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技術文件

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類型 標題 日期
* Data sheet 16-Bit Dual-Supply Bus Transceiver datasheet (Rev. B) 2008年 3月 28日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

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模擬型號

HSPICE Model of SN74AVCBH164245

SCEJ151.ZIP (52 KB) - HSpice Model
模擬型號

SN74AVCBH164245 IBIS Model (Rev. B)

SCEM406B.ZIP (52 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian

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