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交換器與多工器
類比交換器與多工器
通訊協定與匯流排開關與多工器

SN74CBTLV3245A

現行

3.3V、1:1 (SPST)、8 通道通用型 FET 匯流排開關

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產品規格表

SN74CBTLV3245A

現行
產品規格表 立即訂購

產品詳細資料

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
VQFN (RGY) 20 15.75 mm² (4.5 mm × 3.5 mm) SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Standard ’245-type pinout
  • 5Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
  • Standard ’245-type pinout
  • 5Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)

The SN74CBTLV3245A device provides 8 bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maintains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3245A device provides 8 bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maintains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CBTLV3245A Low-Voltage Octal FET Bus Switch datasheet (Rev. N) PDF | HTML 2026/6/10
應用說明 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/6/2
應用說明 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/1
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021/1/6

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EVM-LEADED1 板可用於快速測試和搭建 TI 常見的有引腳封裝  此電路板具備板上配置，可將 TI 的 D、DBQ、DCT、DCU、DDF、DGS、DGV 和 PW 表面黏著封裝轉換為 100mil DIP 排針。     

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模擬型號

HSPICE MODEL OF SN74CBTLV3245A

SCEJ235.ZIP (104 KB) - HSpice 模型
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模擬型號

SN74CBTLV3245A IBIS Model (Rev. B)

SCDM025 (152 KB) - IBIS 模型
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參考設計

TIDM-DELFINO-ETHERCAT — 適用於高效能 MCU 的 EtherCAT 介面參考設計

此參考設計展示了如何將 C2000 Delfino MCU 連接至 EtherCAT™ ET1100 從屬控制器。該介面同時支援去多工地址/資料匯流排，以實現最高頻寬與最低延遲，以及支援以低接腳數進行 EtherCAT 通訊的 SPI 模式。  此從屬控制器可分擔 100Mbps 乙太網路式現場總線通訊的處理工作，從而消除 CPU 的負擔。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGY) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
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