SN74LVC2G34

Name: SN74LVC2G34
Brand: TI
SKU: SN74LVC2G34
Price: 0.054 USD

現行

2 通道 1.65-V 至 5.5-V 緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74LVC2G34 Dual Buffer Gate datasheet (Rev. J) (英文) PDF | HTML

SN74LVC2G34

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

Available in the Texas Instruments NanoFree Package
Supports 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Maximum t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

Available in the Texas Instruments NanoFree Package
Supports 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Maximum t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The SN74LVC2G34 device is a dual buffer gate designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC2G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC2G34 device is a dual buffer gate designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC2G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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	類型	標題		日期
*	Data sheet	SN74LVC2G34 Dual Buffer Gate datasheet (Rev. J)	PDF \| HTML	2015年 10月 30日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021年 7月 26日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)		2003年 11月 14日
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		2003年 11月 6日
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		2002年 12月 18日
	Application note	Texas Instruments Little Logic Application Report		2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002年 8月 29日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002年 6月 13日
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002年 5月 22日
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002年 5月 10日
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002年 3月 27日
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997年 12月 1日
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997年 8月 1日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997年 6月 1日
	Application note	LVC Characterization Information		1996年 12月 1日
	Application note	Input and Output Characteristics of Digital Integrated Circuits		1996年 10月 1日
	Application note	Live Insertion		1996年 10月 1日
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		1996年 9月 1日
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996年 5月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。

使用指南: PDF

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模擬型號

HSPICE MODEL OF SN74LVC2G34

SCEJ194.ZIP (87 KB) - HSpice Model

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模擬型號

SN74LVC2G34 Behavioral SPICE Model

SCEM610.ZIP (7 KB) - PSpice Model

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模擬型號

SN74LVC2G34 IBIS Model (Rev. B)

SCEM255B.ZIP (45 KB) - IBIS Model

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Design guide: PDF

電路圖: PDF

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Design guide: PDF

電路圖: PDF

參考設計

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