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邏輯和電壓轉換
電壓轉換器及電平移位器
電壓轉換器

SN74LVC2T45

現行

具可配置電壓位準移位與 3 態輸出的 2 位元雙供應收發器

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產品規格表

SN74LVC2T45

現行
立即訂購

產品詳細資料

Bits (#) 2 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, I2S, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 3.9 Technology family LVC Supply current (max) (mA) 0.004 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 2 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, I2S, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 3.9 Technology family LVC Supply current (max) (mA) 0.004 Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 8 2.8125 mm² (— mm × — mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm)
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. N) PDF | HTML 2024/6/21
應用說明 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/2
應用說明 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/7/12
應用說明 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/7/3
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021/4/15

設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置，具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置，範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

使用指南: PDF
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模擬型號

SN74LVC2T45 IBIS Model (Rev. A)

SCEM409 (514 KB) - IBIS 模型
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參考設計

TIDA-010026 — 適用於 EnDat2.2 絕對編碼器的耐用介面參考設計

此參考設計展示了與 EnDat 2.2 編碼器的穩健介面。展示 EMC 抗擾性，特別是對快速瞬態干擾，例如逆變器切換雜訊。編碼器電源電壓可配置，並整合短路保護，防止因纜線短路或配線錯誤導致損壞，同時提供診斷回饋以偵測故障。邏輯介面支援 3.3V 至 1.8V I/O。此設計與 TI LaunchPad™ 開發套件相容，可輕鬆評估搭載 C2000™ MCU 的 EnDat2.2。此設計已通過多個 EnDat 2.2 編碼器的測試，電纜長度可達 100 公尺。
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參考設計

TIDA-01401 — 適用於絕對編碼器的高 EMC 耐受性 RS-485 介面參考設計

此高 EMC 抗擾度參考設計展示了一款可用於驅動器與編碼器中的 RS-485 收發器，適用於以下系統：EnDat 2.2、BiSS®、Tamagawa™ 等。EMC 抗擾度——特別是對逆變器開關雜訊的抗擾度——對工業驅動器的位置編碼器回饋系統至關重要。此設計支援 5 至 15V（名義電壓為 12V）輸入範圍，作為輸出電壓供應給編碼器，以因應其廣泛的供電需求。此設計的電源供應器可根據所選編碼器的電壓範圍，提供過電壓與短路保護，避免在纜線短路期間造成損壞。隨附 BoosterPack™ 外掛模組，接頭與 TI LaunchPad™ 開發套件相容，可輕鬆評估 EnDat、BiSS 等 (...)
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參考設計

TIDA-01630 — 適用於 Tamagawa 編碼器的高 EMC 抗擾性 RS485 介面參考設計

EMC 抗擾度，特別是針對變頻器開關雜訊的抗擾度，對於工業驅動器的定位編碼器回饋系統非常重要。此設計展示高 EMC 抗擾性 RS485 收發器解決方案，可同時應用於驅動器和編碼器，例如 Tamagawa™、EnDat 2.2、BiSS® 等。此設計支援 5 V 的寬輸入電壓。具有 3.3 V 邏輯 I/O 訊號和 3.3 V 電源的連接器可直接與主機處理器連接，以執行主控通訊協定並為處理器供電。為符合所選編碼器的供應範圍，此設計可為編碼器提供與 Vin 相同的輸出電壓。此設計的電源供應器可根據所選編碼器的電壓範圍，提供過電壓與短路保護，避免在纜線短路期間造成損壞。此設計已通過 (...)
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參考設計

TIDM-ULTRASONIC-WATER-FLOW-MEASUREMENT — 超音波水流測量參考設計

此超音波水流測量系統非常適合在低至 1.4gpm 的廣泛流量範圍中，提供高準確度的測量。此設計以含離散式類比元件的單一 MCU 為基礎。其採用獨特的專用演算法，在各種操作條件下提高流量測量的穩健性和性能。此設計與適用無線 AMI 網路的 TI RF 外掛評估模組完全相容。

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DSBGA (YZP) 8 Ultra Librarian
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SSOP (DCT) 8 Ultra Librarian
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