TDA2P-ACD
- Architecture designed for ADAS applications
- Video, image, and graphics processing support
- Full-HD video (1920 × 1080p, 60 fps)
- Multiple video input and video output
- Dual Arm® Cortex®-A15 microprocessor subsystem
- Up to two C66x floating-point VLIW DSP
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
- Up to 2.5MB of on-chip L3 RAM
- Level 3 (L3) and Level 4 (L4) interconnects
- Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB supported per EMIF
- Dual Arm® Cortex®-M4 Image Processing Units (IPU)
- Vision AccelerationPac
- Up to Two Embedded Vision Engines (EVEs)
- Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
- IVA-HD subsystem
- Display subsystem
- Display controller with DMA engine and up to three pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
- 2D-graphics accelerator (BB2D) subsystem
- Vivante® GC320 core
- Video Processing Engine (VPE)
- Dual-core PowerVR® SGX544 3D GPU
- Two Video Input Port (VIP) modules
- Support for up to eight multiplexed input ports
- General-Purpose Memory Controller (GPMC)
- Enhanced Direct Memory Access (EDMA) controller
- 2-Port Gigabit Ethernet (GMAC)
- Up to Two Controller Area Network (DCAN) modules
- CAN 2.0B protocol
- Modular Controller Area Network (MCAN) module
- CAN 2.0B protocol with available FD (Flexible Data Rate) functionality
- MIPI CSI-2 camera serial interface
- PCI Express® 3.0 port with integrated PHY
- One 2-lane Gen2-compliant port
- or two 1-lane Gen2-compliant ports
- Sixteen 32-bit general-purpose timers
- 32-Bit MPU watchdog timer
- Ten configurable UART/IrDA/CIR modules
- Four Multichannel Serial Peripheral Interfaces (McSPI)
- Quad SPI interface
- Five Inter-Integrated Circuit (I2C) ports
- SATA interface
- Eight Multichannel Audio Serial Port (McASP) modules
- SuperSpeed USB 3.0 dual-role device
- Three high-speed USB 2.0 dual-role devices
- Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
- Up to 247 General-Purpose I/O (GPIO) pins
- Device security features
- Hardware crypto accelerators and DMA
- Firewalls
- JTAG® lock
- Secure keys
- Secure ROM and boot
- Customer programmable keys and OTP data
- Power, reset, and clock management
- On-Chip debug With CTools technology
- Automotive AEC-Q100 qualified
- 28-nm CMOS technology
- 23 mm × 23 mm, 0.8-mm pitch, 784-Pin BGA (ACD)
TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.
The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.
The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.
TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.
The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.
The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Errata | TDA2P, DRA7xxP, AM574x Package Discontinued and Redesigned (Rev. A) | PDF | HTML | 2025年 10月 28日 |
| * | Errata | TDA2Px Silicon Errata (Rev. B) | PDF | HTML | 2024年 9月 8日 |
| * | Data sheet | TDA2Px ADAS applications processor 23mm package (ACD package) SR1.0 adds APB package notice datasheet (Rev. F) | 2019年 2月 5日 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
- 晶圓廠位置
- 組裝地點