首頁 微控制器 (MCU) 與處理器 微處理器和 DSP 汽車駕駛輔助 SoC
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微控制器 (MCU) 與處理器
微處理器和 DSP
汽車駕駛輔助 SoC

TDA2P-ACD

現行

適用於 ADAS 且具有繪圖、成像處理、視訊和視覺加速選項的高效能 SoC 系列

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產品規格表
使用指南

TDA2P-ACD

現行
產品規格表 立即訂購

產品詳細資料

CPU 2 Arm Cortex-A15 Frequency (MHz) 500, 650, 750, 1176, 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image system processor, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A15 Frequency (MHz) 500, 650, 750, 1176, 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image system processor, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (ACD) 784 529 mm² (23 mm × 23 mm) FCBGA (APB) 784 529 mm² (23 mm × 23 mm)
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Vision AccelerationPac
    • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) modules
    • Support for up to eight multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Up to Two Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol with available FD (Flexible Data Rate) functionality
  • MIPI CSI-2 camera serial interface
  • PCI Express® 3.0 port with integrated PHY
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys and OTP data
  • Power, reset, and clock management
  • On-Chip debug With CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-Pin BGA (ACD)
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Vision AccelerationPac
    • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) modules
    • Support for up to eight multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Up to Two Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol with available FD (Flexible Data Rate) functionality
  • MIPI CSI-2 camera serial interface
  • PCI Express® 3.0 port with integrated PHY
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys and OTP data
  • Power, reset, and clock management
  • On-Chip debug With CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-Pin BGA (ACD)

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TDA2Px ADAS applications processor 23mm package (ACD package) SR1.0 adds APB package notice datasheet (Rev. F) PDF | HTML 2019/2/5
* 使用指南 TDA2Px Technical Reference Manual (Rev. C) 2020/2/25
* 勘誤表 TDA2P, DRA7xxP, AM574x Package Discontinued and Redesigned (Rev. B) PDF | HTML 2026/5/26
* 勘誤表 TDA2Px Silicon Errata (Rev. B) PDF | HTML 2024/9/8
應用說明 Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/5/5
應用說明 IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/8/24
白皮書 Stereo vision- facing the challenges and seeing the opportunities for ADAS (Rev. A) 2020/7/24
白皮書 Paving the way to self-driving cars with ADAS (Rev. A) 2020/7/24
應用說明 AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/1/6
應用說明 Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/6/11
應用說明 TDA2x/TDA2E Performance (Rev. A) PDF | HTML 2019/6/10
應用說明 TDA2Px Performance (Rev. A) 2018/10/22
應用說明 The Implementation of YUV422 Output for SRV 2018/8/2
應用說明 MMC DLL Tuning (Rev. B) 2018/7/31
應用說明 Integrating AUTOSAR on TI SoC: Fundamentals 2018/6/18
應用說明 ECC/EDC on TDAxx (Rev. B) 2018/6/13
應用說明 Sharing VPE Between VISIONSDK and PSDKLA 2018/5/4
使用指南 LP87565C-Q1 and TPS65917-Q1 User’s Guide to Power DRA7xxP and TDA2Pxx (Rev. A) 2018/4/20
應用說明 TMS320C66x XMC Memory Protection 2018/1/31
應用說明 DSS Bit Exact Output (Rev. A) 2018/1/12
應用說明 Flashing Utility - mflash 2018/1/9
應用說明 Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/7
應用說明 A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/3
應用說明 DSS BT656 Workaround for TDA2x (Rev. A) 2017/11/3
功能安全資訊 Safety Features on VisionSDK 2017/10/26
應用說明 Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/9/12
白皮書 Step into next-gen architectures for multi-camera operations in automobiles 2017/6/16
白皮書 Making Cars Safer Through Technology Innovation (Rev. A) 2017/6/7
應用說明 Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
應用說明 Quad Channel Camera Application for Surround View and CMS Camera Systems (Rev. A) 2016/8/23
應用說明 ADAS Power Management 2016/3/7
白皮書 Multicore SoCs stay a step ahead of SoC FPGAs 2016/2/23
白皮書 Surround view camera systems for ADAS (Rev. A) 2015/10/20
應用說明 Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/8/13
白皮書 TI Vision SDK, Optimized Vision Libraries for ADAS Systems 2014/4/14
白皮書 TI Gives Sight to Vision-Enabled Automotive Technologies 2013/10/16
白皮書 Empowering Automotive Vision with TI’s Vision AccelerationPac 2013/10/13

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TDA2PXEVM — TDA2Px 評估模組

TDA2Px EVM 評估平台旨在加快 ADAS 應用的開發速度及縮短上市時間。TDA2Px EVM 是以 TDA2Px 系統單晶片 (SoC) 為基礎，其整合異質、可擴充架構，其中包括 TI 的定點與浮點 TMS320C66x 數位訊號處理器 (DSP) 核心、視覺加速 Pac (EVE) 核心、Arm® Cortex®-A15 MP 核心、3D GPU 核心、H.264 編碼/解碼加速與雙 Cortex-M4 核心。其還整合眾多週邊設備，其中包括適用 LVDS 環景系統的多攝影機介面（並聯及串聯）、CSI-2 埠、顯示器、CAN 和 GigB 乙太網路 AVB。

主 CPU (...)
使用指南: PDF
從：SVTRONICS INC
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軟體開發套件 (SDK)

PROCESSOR-SDK-RADAR — RTOS Processor SDK for Radar

處理器 SDK-Vision (Vision SDK) 和處理器 SDK-Radar (Radar SDK) 是適用於 TDAx 處理器的多處理器軟體開發套件。軟體架構可讓使用者建立不同的 ADAS 應用資料流程，其中包含雷達擷取、雷達處理、視訊擷取、視訊預處理、視訊分析演算法和視訊顯示。.此版本還整合了處理器 SDK Linux，以啟用需要 Linux 和 GPU 的汽車 ADAS 功能和示範。SDK 具備適用 EVE 和 DSP 的基礎驅動器、運算與視覺核心。此外還具有使用 TI 範例演算法的示範使用案例，演練 ADAS SoC 中的不同 CPU (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-VISION — Linux and RTOS Processor SDK for Vision

處理器 SDK-Vision (Vision SDK) 和處理器 SDK-Radar (Radar SDK) 是適用於 TDAx 處理器的多處理器軟體開發套件。軟體架構可讓使用者建立不同的 ADAS 應用資料流程，其中包含雷達擷取、雷達處理、視訊擷取、視訊預處理、視訊分析演算法和視訊顯示。.此版本還整合了處理器 SDK Linux，以啟用需要 Linux 和 GPU 的汽車 ADAS 功能和示範。SDK 具備適用 EVE 和 DSP 的基礎驅動器、運算與視覺核心。此外還具有使用 TI 範例演算法的示範使用案例，演練 ADAS SoC 中的不同 CPU (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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模擬型號

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL 模型
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模擬型號

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS 模型
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模擬型號

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - 熱模型
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (ACD) 784 Ultra Librarian
FCBGA (APB) 784 Ultra Librarian
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