THS3217

現行

DC 至 800-MHz、差動至單端、DAC 輸出放大器

產品詳細資料

Architecture Current FB Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 8 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 15.8 GBW (typ) (MHz) 800 BW at Acl (MHz) 800 Acl, min spec gain (V/V) 3 Slew rate (typ) (V/µs) 5000 Vn at flatband (typ) (nV√Hz) 9 Vn at 1 kHz (typ) (nV√Hz) 40 Iq per channel (typ) (mA) 55 Vos (offset voltage at 25°C) (max) (mV) 18 Rail-to-rail No Features Differential-to-single-ended conversion, Shutdown Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 55 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 58 Iout (typ) (mA) 120 2nd harmonic (dBc) 60 3rd harmonic (dBc) 75 Frequency of harmonic distortion measurement (MHz) 20
Architecture Current FB Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 8 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 15.8 GBW (typ) (MHz) 800 BW at Acl (MHz) 800 Acl, min spec gain (V/V) 3 Slew rate (typ) (V/µs) 5000 Vn at flatband (typ) (nV√Hz) 9 Vn at 1 kHz (typ) (nV√Hz) 40 Iq per channel (typ) (mA) 55 Vos (offset voltage at 25°C) (max) (mV) 18 Rail-to-rail No Features Differential-to-single-ended conversion, Shutdown Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 55 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 58 Iout (typ) (mA) 120 2nd harmonic (dBc) 60 3rd harmonic (dBc) 75 Frequency of harmonic distortion measurement (MHz) 20
VQFN (RGV) 16 16 mm² 4 x 4
  • Input Stage: Internal Gain of 2-V/V
    • Buffered Differential Inputs
    • Single-Ended Low Impedance Output
    • Full-Power Bandwidth: 500-MHz (2 VPP)
  • Output Stage: Gain Externally Configurable
    • Full-Power Bandwidth: 500-MHz (5 VPP)
    • Slew Rate: 5000 V/µs
    • SPDT Input Switch / Multiplexer
  • Full Signal Path: Input Stage + Output Stage
    • HD2 (20 MHz, 5 VPP to 100-Ω Load): –60 dBc
    • HD3 (20 MHz, 5 VPP to 100-Ω Load): –75 dBc
    • 10-VPP Output to 100-Ω Load Using Split
      ±6.5-V Supply
    • 12-VPP Output to Heavy Capacitive Loads Using Single 15-V Supply
  • Internal DC Reference Buffer with Low Impedance Output
  • Power-Supply Range:
    • Split Supply: ±4 V to ±7.9 V
    • Single Supply: 8 V to 15.8 V
  • Input Stage: Internal Gain of 2-V/V
    • Buffered Differential Inputs
    • Single-Ended Low Impedance Output
    • Full-Power Bandwidth: 500-MHz (2 VPP)
  • Output Stage: Gain Externally Configurable
    • Full-Power Bandwidth: 500-MHz (5 VPP)
    • Slew Rate: 5000 V/µs
    • SPDT Input Switch / Multiplexer
  • Full Signal Path: Input Stage + Output Stage
    • HD2 (20 MHz, 5 VPP to 100-Ω Load): –60 dBc
    • HD3 (20 MHz, 5 VPP to 100-Ω Load): –75 dBc
    • 10-VPP Output to 100-Ω Load Using Split
      ±6.5-V Supply
    • 12-VPP Output to Heavy Capacitive Loads Using Single 15-V Supply
  • Internal DC Reference Buffer with Low Impedance Output
  • Power-Supply Range:
    • Split Supply: ±4 V to ±7.9 V
    • Single Supply: 8 V to 15.8 V

The THS3217 combines the key signal-chain components required to interface with a complementary-current output, digital-to-analog converter (DAC). The flexibility provided by this two-stage amplifier system delivers the low distortion, dc-coupled, differential to single-ended signal processing required by a wide range of systems. The input stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS). The wideband, current-feedback, output power stage provides all pins externally for flexible gain setting.

An internal 2×1 multiplexer (mux) to the output power stage noninverting input provides an easy means to select between the internal differential-to-single-ended stage (D2S) output or an external input.

An optional on-chip midsupply buffer provides a wideband, low-output-impedance source for biasing during single-supply operation through the signal-path stages. This feature provides very simple biasing for single-supply, ac-coupled applications operating up to a maximum 15.8-V supply. An external input to this buffer allows for a dc error-correction loop, or a simple output dc offset feature.

A companion device, the THS3215, provides the same functional features at lower quiescent power and bandwidth. The THS3217 and the THS3215 support the emerging high-speed Texas Instruments DACs for AWG applications, such as the DAC38J82.

The THS3217 combines the key signal-chain components required to interface with a complementary-current output, digital-to-analog converter (DAC). The flexibility provided by this two-stage amplifier system delivers the low distortion, dc-coupled, differential to single-ended signal processing required by a wide range of systems. The input stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS). The wideband, current-feedback, output power stage provides all pins externally for flexible gain setting.

An internal 2×1 multiplexer (mux) to the output power stage noninverting input provides an easy means to select between the internal differential-to-single-ended stage (D2S) output or an external input.

An optional on-chip midsupply buffer provides a wideband, low-output-impedance source for biasing during single-supply operation through the signal-path stages. This feature provides very simple biasing for single-supply, ac-coupled applications operating up to a maximum 15.8-V supply. An external input to this buffer allows for a dc error-correction loop, or a simple output dc offset feature.

A companion device, the THS3215, provides the same functional features at lower quiescent power and bandwidth. The THS3217 and the THS3215 support the emerging high-speed Texas Instruments DACs for AWG applications, such as the DAC38J82.

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類型 標題 日期
* Data sheet THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier datasheet (Rev. B) PDF | HTML 2016年 2月 26日
Technical article 3 common questions when designing with high-speed amplifiers PDF | HTML 2020年 7月 17日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
EVM User's guide THS3215EVM and THS3217EVM User's Guide (Rev. A) 2016年 4月 6日
Application note Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日

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開發板

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This evaluation module (EVM) is a demonstration fixture for the THS3217 wideband, differential DAC to single-ended line driver. The EVM provides 50-Ω input and output termination for easy evaluation with common 50-Ω test equipment. The THS3217EVM enables performance evaluation of each (...)
使用指南: PDF
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模擬型號

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SBOMBL0.ZIP (51 KB) - PSpice Model
模擬型號

THS3217 TINA-TI Reference Design

SBOM971.TSC (62 KB) - TINA-TI Reference Design
模擬型號

THS3217 TINA-TI Spice Model

SBOM970.ZIP (15 KB) - TINA-TI Spice Model
計算工具

ANALOG-ENGINEER-CALC — 類比工程師計算機

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計算工具

VOLT-DIVIDER-CALC — Voltage divider calculation tool

The voltage divider calculation tool (VOLT-DIVIDER-CALC) quickly determines a set of resistors for a voltage divider. This KnowledgeBase JavaScript utility can be used to find a set of resistors for a voltage divider to achieve the desired output voltage. VOLT-DIVIDER-CALC can also be used to (...)
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

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使用指南: PDF
參考設計

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In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
Design guide: PDF
電路圖: PDF
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