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數位訊號處理器 (DSP)

TMS320C54CST

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用於用戶端電話語音的數位訊號處理器 (僅限 DSP)

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TMS320C54CST

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產品詳細資料

DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Rating Catalog Operating temperature range (°C) to
DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Rating Catalog Operating temperature range (°C) to
LQFP (PGE) 144 484 mm² 22 x 22
  • On-Chip ROM
    • 128K × 16-Bit Configured for Program Memory
    • Contains 14 TMS320™ DSP Algorithm Standard Compliant Telephony Algorithms
  • 40K x 16-Bit On-Chip RAM Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • CST Software in ROM:
    • Data Transfer (Modem up to V.32BIS 14400 bps)
    • Telephony Signals Processing (DTMF, CPTD, Caller ID)
    • Voice Processing (Echo Canceller, G726, VAD, CNG, AGC)
  • Configurable in Either:
    • Chipset Mode: Stand-Alone Telephony/Data Modem (ROM-Only Code Execution)
    • Flex Mode: Code Execution From RAM, ROM, or External.
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/ Transmitter (UART) With Integrated Baud Rate Generator
    • Integrated Direct Access Arrangement (DAA) Module
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

All trademarks are the property of their respective owners.
TMS320 is a trademark of Texas Instruments.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x is a trademark of Texas Instruments.
  • On-Chip ROM
    • 128K × 16-Bit Configured for Program Memory
    • Contains 14 TMS320™ DSP Algorithm Standard Compliant Telephony Algorithms
  • 40K x 16-Bit On-Chip RAM Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • CST Software in ROM:
    • Data Transfer (Modem up to V.32BIS 14400 bps)
    • Telephony Signals Processing (DTMF, CPTD, Caller ID)
    • Voice Processing (Echo Canceller, G726, VAD, CNG, AGC)
  • Configurable in Either:
    • Chipset Mode: Stand-Alone Telephony/Data Modem (ROM-Only Code Execution)
    • Flex Mode: Code Execution From RAM, ROM, or External.
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/ Transmitter (UART) With Integrated Baud Rate Generator
    • Integrated Direct Access Arrangement (DAA) Module
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

All trademarks are the property of their respective owners.
TMS320 is a trademark of Texas Instruments.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x is a trademark of Texas Instruments.

The 54CST are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.

The 54CST are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.
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類型 標題 日期
* Data sheet TMS320C54CST Client Side Telephony DSP datasheet (Rev. C) 2008年 10月 22日
* Errata TMS320C54CST MicroStar BGA Discontinued and Redesigned 2020年 5月 21日
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
Application note TMS320C54CST Bootloader Technical Reference (Rev. A) 2003年 9月 12日
Product overview Client Side Telephony Product Bulletin (Rev. B) 2003年 7月 11日
User guide TMS320C54x Chip Support Library API Reference Guide (Rev. D) 2003年 5月 5日
User guide Caller ID (CID) Algorithm User's Guide 2003年 3月 18日
User guide Comfort Noise Generator (CNG) Algorithm User's Guide 2003年 3月 18日
User guide Echo Canceller (EC) Algorithm User's Guide 2003年 3月 18日
User guide G726 Algorithm User's Guide 2003年 3月 18日
User guide ModemIntegrator Algorithm User's Guide 2003年 3月 18日
User guide TMS320C54CST Caller ID I & II Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST Data Modem Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST G.165/G.168 Echo Canceller Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST G.726 Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST Universal Multi Tone Detector/Generator Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST V.42/V.42bis Algorithm (Rev. A) 2003年 3月 18日
User guide TMS320C54CST VAD, AGC, CNG Algorithm (Rev. A) 2003年 3月 18日
User guide Universal Multifrequency Tone Detector (UMTD) Algorithm User's Guide 2003年 3月 18日
User guide Universal Multifrequency Tone Generator (UMTG) 2003年 3月 18日
User guide Voice Activity Detector (VAD) Algorithm User's Guide 2003年 3月 18日
Application note Client Side Telephony (CST) Chipset Mode 2003年 1月 6日
User guide Client Side Telephony (CST) Chip Software User's Guide (Rev. A) 2002年 3月 19日
Application note Client Side Telephony (CST) Chip Flex Mode Flex Examples Description 2002年 1月 7日

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