TS2PCIE2212

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4 通道 PCIe 2:1 解多工器/解多工器被動 FET 開關

TS2PCIE2212

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產品詳細資料

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NFBGA (ZAH) 48 25 mm² 5 x 5
  • Offers Bandwidth Allocation of PCI Express™ Signal Using Two-Lane 1:2 Multiplexer/Demultiplexer
  • Vcc Operating Range From 1.7 V to 1.9 V
  • Supports Data Rates of 2.5 Gbps
  • Port-Port Crosstalk (-39 dB at 1.25 GHz)
  • OFF Port Isolation (-38 dB at 1.25 GHz)
  • Low ON-State Resistance (10 Typ)
  • Low Input/Output Capacitance (3.5 pF Typ)
  • Excellent Differential Skew (5 ps Max)
  • Minimal Propagation Delay
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

PCI Express is a trademark of PCI-SIG.

  • Offers Bandwidth Allocation of PCI Express™ Signal Using Two-Lane 1:2 Multiplexer/Demultiplexer
  • Vcc Operating Range From 1.7 V to 1.9 V
  • Supports Data Rates of 2.5 Gbps
  • Port-Port Crosstalk (-39 dB at 1.25 GHz)
  • OFF Port Isolation (-38 dB at 1.25 GHz)
  • Low ON-State Resistance (10 Typ)
  • Low Input/Output Capacitance (3.5 pF Typ)
  • Excellent Differential Skew (5 ps Max)
  • Minimal Propagation Delay
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

PCI Express is a trademark of PCI-SIG.

The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing differential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidth standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank accommodating two sources (source A and source B) and two destinations (destination A and destination B).

When a logic-level low is applied to the control (CTRL) pin, source A is connected to destination A and source B is connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destination B, while source B and destination A are open.

The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing differential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidth standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank accommodating two sources (source A and source B) and two destinations (destination A and destination B).

When a logic-level low is applied to the control (CTRL) pin, source A is connected to destination A and source B is connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destination B, while source B and destination A are open.

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