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ADC31JB68RTAT ACTIVE

16-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

Inventory: 3,071
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material SN
MSL rating / Peak reflow Level-3-260C-168 HR
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View

Packaging information

Package | Pins Package qty | Carrier Operating temperature range (°C)
WQFN (RTA) | 40 250 | SMALL T&R
-40 to 85
Package | Pins WQFN (RTA) | 40
Package qty | Carrier 250 | SMALL T&R
Operating temperature range (°C) -40 to 85
View TI packaging information

Features for the ADC31JB68

  • Single Channel
  • 16-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Small 40-Pin QFN Package (6 x 6 mm)
  • Input Buffer Input Bandwidth (3 dB): 1300 MHz
  • Aperture Jitter: 80 fs
  • On Chip Clock Divider: /1, /2, /4
  • On Chip Dither
  • Consistent Dynamic Performance Using Foreground and Background Calibration
  • Input Amplitude and Phase Adjustment
  • Input Full Scale: 1.7 Vpp
  • Power Supplies: 1.2/1.8/3 V
  • JESD204B Interface
    • Subclass 1Compliant
    • 2 Lanes at 5 Gbps
  • Support for Multi-chip Synchronization
  • Key Specifications
    • Power Dissipation: 915 mW at 500 Msps
    • Performance at fin = 210 MHz at –1 dBFS
      • SNR: 69.3 dBFS
      • NSD: –153.3 dBFS/Hz
      • SFDR: 80 dBc
      • Non-HD2,HD3: –91 dBFS
    • Performance at fin = 450 MHz at –1dBFS
      • SNR: 67 dBFS
      • NSD: –151 dBFS/Hz
      • SFDR: 77 dBc HD2,3
      • Non-HD2,HD3: –89 dBFS

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Description for the ADC31JB68

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digitalconverter (ADC). The buffered analog input provides uniform input impedance across a wide frequencyrange while minimizing sample-and-hold glitch energy. This device is designed to sample inputsignals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large inputfrequency range with very-low power consumption. On-chip dither provides an very-clean noise floor.Embedded foreground and background calibration provides consistent performance over the temperaturerange, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on eachof two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.


Pricing


Qty Price (USD)
1+ $159.720