Product details


Sample rate (Max) (MSPS) 500 Resolution (Bits) 16 Number of input channels 1 Interface JESD204B Analog input BW (MHz) 1300 Features High Performance Rating Catalog Input range (Vp-p) 1.7 Power consumption (Typ) (mW) 915 Architecture Pipeline SNR (dB) 70.6 ENOB (Bits) 11.3 SFDR (dB) 83 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

WQFN (RTA) 40 36 mm² 6 x 6 open-in-new Find other High-speed ADCs (>10MSPS)


  • Single Channel
  • 16-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Small 40-Pin QFN Package (6 x 6 mm)
  • Input Buffer Input Bandwidth (3 dB): 1300 MHz
  • Aperture Jitter: 80 fs
  • On Chip Clock Divider: /1, /2, /4
  • On Chip Dither
  • Consistent Dynamic Performance Using Foreground and Background Calibration
  • Input Amplitude and Phase Adjustment
  • Input Full Scale: 1.7 Vpp
  • Power Supplies: 1.2/1.8/3 V
  • JESD204B Interface
    • Subclass 1 Compliant
    • 2 Lanes at 5 Gbps
  • Support for Multi-chip Synchronization
  • Key Specifications
    • Power Dissipation: 915 mW at 500 Msps
    • Performance at fin = 210 MHz at –1 dBFS
      • SNR: 69.3 dBFS
      • NSD: –153.3 dBFS/Hz
      • SFDR: 80 dBc
      • Non-HD2,HD3: –91 dBFS
    • Performance at fin = 450 MHz at –1 dBFS
      • SNR: 67 dBFS
      • NSD: –151 dBFS/Hz
      • SFDR: 77 dBc HD2,3
      • Non-HD2,HD3: –89 dBFS

All trademarks are the property of their respective owners.

open-in-new Find other High-speed ADCs (>10MSPS)


The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 1
Type Title Date
* Datasheet ADC31JB68 Single-channel, 16-bit, 500-MSPS analog-to-digital converter datasheet (Rev. B) Jan. 22, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADC31JB68EVM is an evaluation board used to evaluate the ADC31JB68 analog-to-digital converter (ADC) from Texas Instruments. The ADC31JB68 is a single-channel 16-bit ADC capable of operating at sampling rates up to 500 Mega Samples Per Second (MSPS) with outputs featuring a standard JESD204B (...)


  • Transformer-coupled signal input network allowing a single-ended signal source
  • LMK4828 system clock generator that generates the FPGA reference clock for the high speed serial interface
  • Default Transformer-coupled clock input network to test the ADC performance with a very low-noise clock
  • High speed (...)

Sundance Digital Signal Processing Inc. FMC-ADC500-5 high pin count FMC module
Provided by Sundance Digital Signal Processing Inc.
FMC-ADC500-5 is a high pin count (HPC) FMC module with 5 ADC channels each running at up to 500MS/s with a dynamic range of 16 bits. The module has 5 ADC31JB68 ICs from Texas Instruments together with an HMC7044 from ADI which is the source of clocks feeding the ADCs. Provision for external clock (...)
SLAC707.ZIP (169768 KB)

Software development

High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SLAM272.ZIP (25 KB) - IBIS Model

Reference designs

160-MHz Bandwidth Wireless Signal Tester Reference Design
TIDA-00988 — This reference design implements an IF subsystem for a standard wireless signal tester with an active balun-amplifier (LMH5401), LC bandpass filter, 16-bit ADC (ADC31JB68) and clock cleaner and generator PLL (LMK04828). Measurements using modulated signals demonstrate reception of the signal with (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RTA) 40 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​