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High-speed ADCs (≥10 MSPS)

ADC31JB68

ACTIVE

16-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

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ADC3569 ACTIVE 16-bit one-channel 500MSPS ADC with LVDS interface and up to 32768x decimation Lower power, higher SNR, LVDS interface

ADC31JB68

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 1300 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 915 Architecture Pipeline SNR (dB) 70.6 ENOB (Bits) 11.3 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 1300 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 915 Architecture Pipeline SNR (dB) 70.6 ENOB (Bits) 11.3 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
WQFN (RTA) 40 36 mm² 6 x 6
  • Single Channel
  • 16-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Small 40-Pin QFN Package (6 x 6 mm)
  • Input Buffer Input Bandwidth (3 dB): 1300 MHz
  • Aperture Jitter: 80 fs
  • On Chip Clock Divider: /1, /2, /4
  • On Chip Dither
  • Consistent Dynamic Performance Using Foreground and Background Calibration
  • Input Amplitude and Phase Adjustment
  • Input Full Scale: 1.7 Vpp
  • Power Supplies: 1.2/1.8/3 V
  • JESD204B Interface
    • Subclass 1 Compliant
    • 2 Lanes at 5 Gbps
  • Support for Multi-chip Synchronization
  • Key Specifications
    • Power Dissipation: 915 mW at 500 Msps
    • Performance at fin = 210 MHz at –1 dBFS
      • SNR: 69.3 dBFS
      • NSD: –153.3 dBFS/Hz
      • SFDR: 80 dBc
      • Non-HD2,HD3: –91 dBFS
    • Performance at fin = 450 MHz at –1 dBFS
      • SNR: 67 dBFS
      • NSD: –151 dBFS/Hz
      • SFDR: 77 dBc HD2,3
      • Non-HD2,HD3: –89 dBFS
  • Single Channel
  • 16-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Small 40-Pin QFN Package (6 x 6 mm)
  • Input Buffer Input Bandwidth (3 dB): 1300 MHz
  • Aperture Jitter: 80 fs
  • On Chip Clock Divider: /1, /2, /4
  • On Chip Dither
  • Consistent Dynamic Performance Using Foreground and Background Calibration
  • Input Amplitude and Phase Adjustment
  • Input Full Scale: 1.7 Vpp
  • Power Supplies: 1.2/1.8/3 V
  • JESD204B Interface
    • Subclass 1 Compliant
    • 2 Lanes at 5 Gbps
  • Support for Multi-chip Synchronization
  • Key Specifications
    • Power Dissipation: 915 mW at 500 Msps
    • Performance at fin = 210 MHz at –1 dBFS
      • SNR: 69.3 dBFS
      • NSD: –153.3 dBFS/Hz
      • SFDR: 80 dBc
      • Non-HD2,HD3: –91 dBFS
    • Performance at fin = 450 MHz at –1 dBFS
      • SNR: 67 dBFS
      • NSD: –151 dBFS/Hz
      • SFDR: 77 dBc HD2,3
      • Non-HD2,HD3: –89 dBFS

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.
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* Data sheet ADC31JB68 Single-channel, 16-bit, 500-MSPS analog-to-digital converter datasheet (Rev. B) PDF | HTML 22 Jan 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SDSP-3P-FMC-ADC500-5 — Sundance Digital Signal Processing Inc. FMC-ADC500-5 high pin count FMC module

FMC-ADC500-5 is a high pin count (HPC) FMC module with 5 ADC channels each running at up to 500MS/s with a dynamic range of 16 bits. The module has 5 ADC31JB68 ICs from Texas Instruments together with an HMC7044 from ADI which is the source of clocks feeding the ADCs. Provision for external clock (...)
From: Sundance Digital Signal Processing Inc.
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Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

Supported products & hardware
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GUI for evaluation module (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware
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GUI for evaluation module (EVM)

SLAC707 — ADC31JB68EVM Configuration GUI

Supported products & hardware

Supported products & hardware
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Simulation model

ADC31JB68 IBIS Model

SLAM272.ZIP (25 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-00988 — 160-MHz Bandwidth Wireless Signal Tester Reference Design

This reference design implements an IF subsystem for a standard wireless signal tester with an active balun-amplifier (LMH5401), LC bandpass filter, 16-bit ADC (ADC31JB68) and clock cleaner and generator PLL (LMK04828). Measurements using modulated signals demonstrate reception of the signal with (...)
Design guide: PDF
Schematic: PDF
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WQFN (RTA) 40 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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