The TIDEP-0085 reference design implements a Simple Open Real-Time Ethernet (SORTE) master with the Programmable Real-time Unit and Industrial Communication Subsystem (PRU-ICSS). SORTE enables customer applications to exchange process data between the master and devices in a 4-µs cycle time. The design contains open source PRU firmware to enable customer to differentiate their products.
The SORTE protocol includes device discovery, parametrization, PHY and cable delay measurement, synchronization and process data exchange.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
The AM3359 Industrial Communications Engine (ICE) is a development platform targeted for systems that specifically focus on the industrial communications capabilities of the Sitara AM335x Arm® Cortex™-A8 processors.
The AM335x Arm Cortex-A8 processors integrate the Programmable Real-time Unit (PRU) (...)
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Simple Open Real-Time Ethernet (SORTE) Master With PRU-ICSS Reference Design | May 01, 2017 | |
| More literature | Emulation Wiki -- In-depth technical and "how-to" articles, FAQs, etc. | Mar. 24, 2011 |
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